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comparison test/CodeGen/Mips/llvm-ir/ashr.ll @ 134:3a76565eade5 LLVM5.0.1

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update 5.0.1
author mir3636
date Sat, 17 Feb 2018 09:57:20 +0900
parents 803732b1fca8
children c2174574ed3a
comparison
equal deleted inserted replaced
133:c60214abe0e8 134:3a76565eade5
1 ; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: -check-prefixes=ALL,GP32,M2 2 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 -relocation-model=pic | FileCheck %s \
3 ; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ 3 ; RUN: -check-prefix=MIPS
4 ; RUN: -check-prefixes=ALL,GP32,32R1-R5 4 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 -relocation-model=pic | FileCheck %s \
5 ; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ 5 ; RUN: -check-prefix=MIPS32
6 ; RUN: -check-prefixes=ALL,GP32,32R1-R5 6 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \
7 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ 7 ; RUN: -check-prefix=32R2
8 ; RUN: -check-prefixes=ALL,GP32,32R1-R5 8 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \
9 ; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ 9 ; RUN: -check-prefix=32R2
10 ; RUN: -check-prefixes=ALL,GP32,32R1-R5 10 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \
11 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ 11 ; RUN: -check-prefix=32R2
12 ; RUN: -check-prefixes=ALL,GP32,32R6 12 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \
13 ; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ 13 ; RUN: -check-prefix=32R6
14 ; RUN: -check-prefixes=ALL,GP64,M3 14 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 -relocation-model=pic | FileCheck %s \
15 ; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ 15 ; RUN: -check-prefix=MIPS3
16 ; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 16 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 -relocation-model=pic | FileCheck %s \
17 ; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ 17 ; RUN: -check-prefix=MIPS64
18 ; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 18 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 -relocation-model=pic | FileCheck %s \
19 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ 19 ; RUN: -check-prefix=MIPS64
20 ; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 20 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \
21 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ 21 ; RUN: -check-prefix=MIPS64R2
22 ; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 22 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \
23 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ 23 ; RUN: -check-prefix=MIPS64R2
24 ; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 24 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \
25 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ 25 ; RUN: -check-prefix=MIPS64R2
26 ; RUN: -check-prefixes=ALL,GP64,64R6 26 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \
27 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ 27 ; RUN: -check-prefix=MIPS64R6
28 ; RUN: -check-prefixes=ALL,MM,MMR3 28 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \
29 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ 29 ; RUN: -check-prefix=MMR3
30 ; RUN: -check-prefixes=ALL,MM,MMR6 30 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
31 ; RUN: -check-prefix=MMR6
31 32
32 define signext i1 @ashr_i1(i1 signext %a, i1 signext %b) { 33 define signext i1 @ashr_i1(i1 signext %a, i1 signext %b) {
34 ; MIPS-LABEL: ashr_i1:
35 ; MIPS: # %bb.0: # %entry
36 ; MIPS-NEXT: jr $ra
37 ; MIPS-NEXT: move $2, $4
38 ;
39 ; MIPS32-LABEL: ashr_i1:
40 ; MIPS32: # %bb.0: # %entry
41 ; MIPS32-NEXT: jr $ra
42 ; MIPS32-NEXT: move $2, $4
43 ;
44 ; 32R2-LABEL: ashr_i1:
45 ; 32R2: # %bb.0: # %entry
46 ; 32R2-NEXT: jr $ra
47 ; 32R2-NEXT: move $2, $4
48 ;
49 ; 32R6-LABEL: ashr_i1:
50 ; 32R6: # %bb.0: # %entry
51 ; 32R6-NEXT: jr $ra
52 ; 32R6-NEXT: move $2, $4
53 ;
54 ; MIPS3-LABEL: ashr_i1:
55 ; MIPS3: # %bb.0: # %entry
56 ; MIPS3-NEXT: jr $ra
57 ; MIPS3-NEXT: move $2, $4
58 ;
59 ; MIPS64-LABEL: ashr_i1:
60 ; MIPS64: # %bb.0: # %entry
61 ; MIPS64-NEXT: jr $ra
62 ; MIPS64-NEXT: move $2, $4
63 ;
64 ; MIPS64R2-LABEL: ashr_i1:
65 ; MIPS64R2: # %bb.0: # %entry
66 ; MIPS64R2-NEXT: jr $ra
67 ; MIPS64R2-NEXT: move $2, $4
68 ;
69 ; MIPS64R6-LABEL: ashr_i1:
70 ; MIPS64R6: # %bb.0: # %entry
71 ; MIPS64R6-NEXT: jr $ra
72 ; MIPS64R6-NEXT: move $2, $4
73 ;
74 ; MMR3-LABEL: ashr_i1:
75 ; MMR3: # %bb.0: # %entry
76 ; MMR3-NEXT: move $2, $4
77 ; MMR3-NEXT: jrc $ra
78 ;
79 ; MMR6-LABEL: ashr_i1:
80 ; MMR6: # %bb.0: # %entry
81 ; MMR6-NEXT: move $2, $4
82 ; MMR6-NEXT: jrc $ra
33 entry: 83 entry:
34 ; ALL-LABEL: ashr_i1:
35
36 ; ALL: move $2, $4
37
38 %r = ashr i1 %a, %b 84 %r = ashr i1 %a, %b
39 ret i1 %r 85 ret i1 %r
40 } 86 }
41 87
42 define signext i8 @ashr_i8(i8 signext %a, i8 signext %b) { 88 define signext i8 @ashr_i8(i8 signext %a, i8 signext %b) {
89 ; MIPS-LABEL: ashr_i8:
90 ; MIPS: # %bb.0: # %entry
91 ; MIPS-NEXT: andi $1, $5, 255
92 ; MIPS-NEXT: jr $ra
93 ; MIPS-NEXT: srav $2, $4, $1
94 ;
95 ; MIPS32-LABEL: ashr_i8:
96 ; MIPS32: # %bb.0: # %entry
97 ; MIPS32-NEXT: andi $1, $5, 255
98 ; MIPS32-NEXT: jr $ra
99 ; MIPS32-NEXT: srav $2, $4, $1
100 ;
101 ; 32R2-LABEL: ashr_i8:
102 ; 32R2: # %bb.0: # %entry
103 ; 32R2-NEXT: andi $1, $5, 255
104 ; 32R2-NEXT: jr $ra
105 ; 32R2-NEXT: srav $2, $4, $1
106 ;
107 ; 32R6-LABEL: ashr_i8:
108 ; 32R6: # %bb.0: # %entry
109 ; 32R6-NEXT: andi $1, $5, 255
110 ; 32R6-NEXT: jr $ra
111 ; 32R6-NEXT: srav $2, $4, $1
112 ;
113 ; MIPS3-LABEL: ashr_i8:
114 ; MIPS3: # %bb.0: # %entry
115 ; MIPS3-NEXT: andi $1, $5, 255
116 ; MIPS3-NEXT: jr $ra
117 ; MIPS3-NEXT: srav $2, $4, $1
118 ;
119 ; MIPS64-LABEL: ashr_i8:
120 ; MIPS64: # %bb.0: # %entry
121 ; MIPS64-NEXT: andi $1, $5, 255
122 ; MIPS64-NEXT: jr $ra
123 ; MIPS64-NEXT: srav $2, $4, $1
124 ;
125 ; MIPS64R2-LABEL: ashr_i8:
126 ; MIPS64R2: # %bb.0: # %entry
127 ; MIPS64R2-NEXT: andi $1, $5, 255
128 ; MIPS64R2-NEXT: jr $ra
129 ; MIPS64R2-NEXT: srav $2, $4, $1
130 ;
131 ; MIPS64R6-LABEL: ashr_i8:
132 ; MIPS64R6: # %bb.0: # %entry
133 ; MIPS64R6-NEXT: andi $1, $5, 255
134 ; MIPS64R6-NEXT: jr $ra
135 ; MIPS64R6-NEXT: srav $2, $4, $1
136 ;
137 ; MMR3-LABEL: ashr_i8:
138 ; MMR3: # %bb.0: # %entry
139 ; MMR3-NEXT: andi16 $2, $5, 255
140 ; MMR3-NEXT: jr $ra
141 ; MMR3-NEXT: srav $2, $4, $2
142 ;
143 ; MMR6-LABEL: ashr_i8:
144 ; MMR6: # %bb.0: # %entry
145 ; MMR6-NEXT: andi16 $2, $5, 255
146 ; MMR6-NEXT: srav $2, $4, $2
147 ; MMR6-NEXT: jrc $ra
43 entry: 148 entry:
44 ; ALL-LABEL: ashr_i8:
45
46 ; FIXME: The andi instruction is redundant. 149 ; FIXME: The andi instruction is redundant.
47 ; GP32: andi $[[T0:[0-9]+]], $5, 255
48 ; GP64: andi $[[T0:[0-9]+]], $5, 255
49 ; MM: andi16 $[[T0:[0-9]+]], $5, 255
50 ; ALL: srav $2, $4, $[[T0]]
51
52 %r = ashr i8 %a, %b 150 %r = ashr i8 %a, %b
53 ret i8 %r 151 ret i8 %r
54 } 152 }
55 153
56 define signext i16 @ashr_i16(i16 signext %a, i16 signext %b) { 154 define signext i16 @ashr_i16(i16 signext %a, i16 signext %b) {
155 ; MIPS-LABEL: ashr_i16:
156 ; MIPS: # %bb.0: # %entry
157 ; MIPS-NEXT: andi $1, $5, 65535
158 ; MIPS-NEXT: jr $ra
159 ; MIPS-NEXT: srav $2, $4, $1
160 ;
161 ; MIPS32-LABEL: ashr_i16:
162 ; MIPS32: # %bb.0: # %entry
163 ; MIPS32-NEXT: andi $1, $5, 65535
164 ; MIPS32-NEXT: jr $ra
165 ; MIPS32-NEXT: srav $2, $4, $1
166 ;
167 ; 32R2-LABEL: ashr_i16:
168 ; 32R2: # %bb.0: # %entry
169 ; 32R2-NEXT: andi $1, $5, 65535
170 ; 32R2-NEXT: jr $ra
171 ; 32R2-NEXT: srav $2, $4, $1
172 ;
173 ; 32R6-LABEL: ashr_i16:
174 ; 32R6: # %bb.0: # %entry
175 ; 32R6-NEXT: andi $1, $5, 65535
176 ; 32R6-NEXT: jr $ra
177 ; 32R6-NEXT: srav $2, $4, $1
178 ;
179 ; MIPS3-LABEL: ashr_i16:
180 ; MIPS3: # %bb.0: # %entry
181 ; MIPS3-NEXT: andi $1, $5, 65535
182 ; MIPS3-NEXT: jr $ra
183 ; MIPS3-NEXT: srav $2, $4, $1
184 ;
185 ; MIPS64-LABEL: ashr_i16:
186 ; MIPS64: # %bb.0: # %entry
187 ; MIPS64-NEXT: andi $1, $5, 65535
188 ; MIPS64-NEXT: jr $ra
189 ; MIPS64-NEXT: srav $2, $4, $1
190 ;
191 ; MIPS64R2-LABEL: ashr_i16:
192 ; MIPS64R2: # %bb.0: # %entry
193 ; MIPS64R2-NEXT: andi $1, $5, 65535
194 ; MIPS64R2-NEXT: jr $ra
195 ; MIPS64R2-NEXT: srav $2, $4, $1
196 ;
197 ; MIPS64R6-LABEL: ashr_i16:
198 ; MIPS64R6: # %bb.0: # %entry
199 ; MIPS64R6-NEXT: andi $1, $5, 65535
200 ; MIPS64R6-NEXT: jr $ra
201 ; MIPS64R6-NEXT: srav $2, $4, $1
202 ;
203 ; MMR3-LABEL: ashr_i16:
204 ; MMR3: # %bb.0: # %entry
205 ; MMR3-NEXT: andi16 $2, $5, 65535
206 ; MMR3-NEXT: jr $ra
207 ; MMR3-NEXT: srav $2, $4, $2
208 ;
209 ; MMR6-LABEL: ashr_i16:
210 ; MMR6: # %bb.0: # %entry
211 ; MMR6-NEXT: andi16 $2, $5, 65535
212 ; MMR6-NEXT: srav $2, $4, $2
213 ; MMR6-NEXT: jrc $ra
57 entry: 214 entry:
58 ; ALL-LABEL: ashr_i16:
59
60 ; FIXME: The andi instruction is redundant. 215 ; FIXME: The andi instruction is redundant.
61 ; GP32: andi $[[T0:[0-9]+]], $5, 65535
62 ; GP64: andi $[[T0:[0-9]+]], $5, 65535
63 ; MM: andi16 $[[T0:[0-9]+]], $5, 65535
64 ; ALL: srav $2, $4, $[[T0]]
65
66 %r = ashr i16 %a, %b 216 %r = ashr i16 %a, %b
67 ret i16 %r 217 ret i16 %r
68 } 218 }
69 219
70 define signext i32 @ashr_i32(i32 signext %a, i32 signext %b) { 220 define signext i32 @ashr_i32(i32 signext %a, i32 signext %b) {
221 ; MIPS-LABEL: ashr_i32:
222 ; MIPS: # %bb.0: # %entry
223 ; MIPS-NEXT: jr $ra
224 ; MIPS-NEXT: srav $2, $4, $5
225 ;
226 ; MIPS32-LABEL: ashr_i32:
227 ; MIPS32: # %bb.0: # %entry
228 ; MIPS32-NEXT: jr $ra
229 ; MIPS32-NEXT: srav $2, $4, $5
230 ;
231 ; 32R2-LABEL: ashr_i32:
232 ; 32R2: # %bb.0: # %entry
233 ; 32R2-NEXT: jr $ra
234 ; 32R2-NEXT: srav $2, $4, $5
235 ;
236 ; 32R6-LABEL: ashr_i32:
237 ; 32R6: # %bb.0: # %entry
238 ; 32R6-NEXT: jr $ra
239 ; 32R6-NEXT: srav $2, $4, $5
240 ;
241 ; MIPS3-LABEL: ashr_i32:
242 ; MIPS3: # %bb.0: # %entry
243 ; MIPS3-NEXT: jr $ra
244 ; MIPS3-NEXT: srav $2, $4, $5
245 ;
246 ; MIPS64-LABEL: ashr_i32:
247 ; MIPS64: # %bb.0: # %entry
248 ; MIPS64-NEXT: jr $ra
249 ; MIPS64-NEXT: srav $2, $4, $5
250 ;
251 ; MIPS64R2-LABEL: ashr_i32:
252 ; MIPS64R2: # %bb.0: # %entry
253 ; MIPS64R2-NEXT: jr $ra
254 ; MIPS64R2-NEXT: srav $2, $4, $5
255 ;
256 ; MIPS64R6-LABEL: ashr_i32:
257 ; MIPS64R6: # %bb.0: # %entry
258 ; MIPS64R6-NEXT: jr $ra
259 ; MIPS64R6-NEXT: srav $2, $4, $5
260 ;
261 ; MMR3-LABEL: ashr_i32:
262 ; MMR3: # %bb.0: # %entry
263 ; MMR3-NEXT: jr $ra
264 ; MMR3-NEXT: srav $2, $4, $5
265 ;
266 ; MMR6-LABEL: ashr_i32:
267 ; MMR6: # %bb.0: # %entry
268 ; MMR6-NEXT: srav $2, $4, $5
269 ; MMR6-NEXT: jrc $ra
71 entry: 270 entry:
72 ; ALL-LABEL: ashr_i32:
73
74 ; ALL: srav $2, $4, $5
75
76 %r = ashr i32 %a, %b 271 %r = ashr i32 %a, %b
77 ret i32 %r 272 ret i32 %r
78 } 273 }
79 274
80 define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) { 275 define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) {
276 ; MIPS-LABEL: ashr_i64:
277 ; MIPS: # %bb.0: # %entry
278 ; MIPS-NEXT: srav $2, $4, $7
279 ; MIPS-NEXT: andi $6, $7, 32
280 ; MIPS-NEXT: beqz $6, $BB4_3
281 ; MIPS-NEXT: move $3, $2
282 ; MIPS-NEXT: # %bb.1: # %entry
283 ; MIPS-NEXT: bnez $6, $BB4_4
284 ; MIPS-NEXT: nop
285 ; MIPS-NEXT: $BB4_2: # %entry
286 ; MIPS-NEXT: jr $ra
287 ; MIPS-NEXT: nop
288 ; MIPS-NEXT: $BB4_3: # %entry
289 ; MIPS-NEXT: srlv $1, $5, $7
290 ; MIPS-NEXT: not $3, $7
291 ; MIPS-NEXT: sll $5, $4, 1
292 ; MIPS-NEXT: sllv $3, $5, $3
293 ; MIPS-NEXT: beqz $6, $BB4_2
294 ; MIPS-NEXT: or $3, $3, $1
295 ; MIPS-NEXT: $BB4_4:
296 ; MIPS-NEXT: jr $ra
297 ; MIPS-NEXT: sra $2, $4, 31
298 ;
299 ; MIPS32-LABEL: ashr_i64:
300 ; MIPS32: # %bb.0: # %entry
301 ; MIPS32-NEXT: srlv $1, $5, $7
302 ; MIPS32-NEXT: not $2, $7
303 ; MIPS32-NEXT: sll $3, $4, 1
304 ; MIPS32-NEXT: sllv $2, $3, $2
305 ; MIPS32-NEXT: or $3, $2, $1
306 ; MIPS32-NEXT: srav $2, $4, $7
307 ; MIPS32-NEXT: andi $1, $7, 32
308 ; MIPS32-NEXT: movn $3, $2, $1
309 ; MIPS32-NEXT: sra $4, $4, 31
310 ; MIPS32-NEXT: jr $ra
311 ; MIPS32-NEXT: movn $2, $4, $1
312 ;
313 ; 32R2-LABEL: ashr_i64:
314 ; 32R2: # %bb.0: # %entry
315 ; 32R2-NEXT: srlv $1, $5, $7
316 ; 32R2-NEXT: not $2, $7
317 ; 32R2-NEXT: sll $3, $4, 1
318 ; 32R2-NEXT: sllv $2, $3, $2
319 ; 32R2-NEXT: or $3, $2, $1
320 ; 32R2-NEXT: srav $2, $4, $7
321 ; 32R2-NEXT: andi $1, $7, 32
322 ; 32R2-NEXT: movn $3, $2, $1
323 ; 32R2-NEXT: sra $4, $4, 31
324 ; 32R2-NEXT: jr $ra
325 ; 32R2-NEXT: movn $2, $4, $1
326 ;
327 ; 32R6-LABEL: ashr_i64:
328 ; 32R6: # %bb.0: # %entry
329 ; 32R6-NEXT: srav $1, $4, $7
330 ; 32R6-NEXT: andi $3, $7, 32
331 ; 32R6-NEXT: seleqz $2, $1, $3
332 ; 32R6-NEXT: sra $6, $4, 31
333 ; 32R6-NEXT: selnez $6, $6, $3
334 ; 32R6-NEXT: or $2, $6, $2
335 ; 32R6-NEXT: srlv $5, $5, $7
336 ; 32R6-NEXT: not $6, $7
337 ; 32R6-NEXT: sll $4, $4, 1
338 ; 32R6-NEXT: sllv $4, $4, $6
339 ; 32R6-NEXT: or $4, $4, $5
340 ; 32R6-NEXT: seleqz $4, $4, $3
341 ; 32R6-NEXT: selnez $1, $1, $3
342 ; 32R6-NEXT: jr $ra
343 ; 32R6-NEXT: or $3, $1, $4
344 ;
345 ; MIPS3-LABEL: ashr_i64:
346 ; MIPS3: # %bb.0: # %entry
347 ; MIPS3-NEXT: jr $ra
348 ; MIPS3-NEXT: dsrav $2, $4, $5
349 ;
350 ; MIPS64-LABEL: ashr_i64:
351 ; MIPS64: # %bb.0: # %entry
352 ; MIPS64-NEXT: jr $ra
353 ; MIPS64-NEXT: dsrav $2, $4, $5
354 ;
355 ; MIPS64R2-LABEL: ashr_i64:
356 ; MIPS64R2: # %bb.0: # %entry
357 ; MIPS64R2-NEXT: jr $ra
358 ; MIPS64R2-NEXT: dsrav $2, $4, $5
359 ;
360 ; MIPS64R6-LABEL: ashr_i64:
361 ; MIPS64R6: # %bb.0: # %entry
362 ; MIPS64R6-NEXT: jr $ra
363 ; MIPS64R6-NEXT: dsrav $2, $4, $5
364 ;
365 ; MMR3-LABEL: ashr_i64:
366 ; MMR3: # %bb.0: # %entry
367 ; MMR3-NEXT: srlv $2, $5, $7
368 ; MMR3-NEXT: not16 $3, $7
369 ; MMR3-NEXT: sll16 $5, $4, 1
370 ; MMR3-NEXT: sllv $3, $5, $3
371 ; MMR3-NEXT: or16 $3, $2
372 ; MMR3-NEXT: srav $2, $4, $7
373 ; MMR3-NEXT: andi16 $5, $7, 32
374 ; MMR3-NEXT: movn $3, $2, $5
375 ; MMR3-NEXT: sra $1, $4, 31
376 ; MMR3-NEXT: jr $ra
377 ; MMR3-NEXT: movn $2, $1, $5
378 ;
379 ; MMR6-LABEL: ashr_i64:
380 ; MMR6: # %bb.0: # %entry
381 ; MMR6-NEXT: srav $1, $4, $7
382 ; MMR6-NEXT: andi16 $3, $7, 32
383 ; MMR6-NEXT: seleqz $2, $1, $3
384 ; MMR6-NEXT: sra $6, $4, 31
385 ; MMR6-NEXT: selnez $6, $6, $3
386 ; MMR6-NEXT: or $2, $6, $2
387 ; MMR6-NEXT: srlv $5, $5, $7
388 ; MMR6-NEXT: not16 $6, $7
389 ; MMR6-NEXT: sll16 $4, $4, 1
390 ; MMR6-NEXT: sllv $4, $4, $6
391 ; MMR6-NEXT: or $4, $4, $5
392 ; MMR6-NEXT: seleqz $4, $4, $3
393 ; MMR6-NEXT: selnez $1, $1, $3
394 ; MMR6-NEXT: or $3, $1, $4
395 ; MMR6-NEXT: jrc $ra
81 entry: 396 entry:
82 ; ALL-LABEL: ashr_i64:
83
84 ; M2: srav $[[T0:[0-9]+]], $4, $7
85 ; M2: andi $[[T1:[0-9]+]], $7, 32
86 ; M2: beqz $[[T1]], $[[BB0:BB[0-9_]+]]
87 ; M2: move $3, $[[T0]]
88 ; M2: bnez $[[T1]], $[[BB1:BB[0-9_]+]]
89 ; M2: nop
90 ; M2: $[[EXIT:BB[0-9_]+]]:
91 ; M2: jr $ra
92 ; M2: nop
93 ; M2: $[[BB0]]:
94 ; M2: srlv $[[T2:[0-9]+]], $5, $7
95 ; M2: not $[[T3:[0-9]+]], $7
96 ; M2: sll $[[T4:[0-9]+]], $4, 1
97 ; M2: sllv $[[T5:[0-9]+]], $[[T4]], $[[T3]]
98 ; M2: beqz $[[T1]], $[[EXIT]]
99 ; M2: or $3, $[[T3]], $[[T2]]
100 ; M2: $[[BB1]]:
101 ; M2: jr $ra
102 ; M2: sra $2, $4, 31
103
104 ; 32R1-R5: srlv $[[T0:[0-9]+]], $5, $7
105 ; 32R1-R5: not $[[T1:[0-9]+]], $7
106 ; 32R1-R5: sll $[[T2:[0-9]+]], $4, 1
107 ; 32R1-R5: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
108 ; 32R1-R5: or $3, $[[T3]], $[[T0]]
109 ; 32R1-R5: srav $[[T4:[0-9]+]], $4, $7
110 ; 32R1-R5: andi $[[T5:[0-9]+]], $7, 32
111 ; 32R1-R5: movn $3, $[[T4]], $[[T5]]
112 ; 32R1-R5: sra $4, $4, 31
113 ; 32R1-R5: jr $ra
114 ; 32R1-R5: movn $2, $4, $[[T5]]
115
116 ; 32R6: srav $[[T0:[0-9]+]], $4, $7
117 ; 32R6: andi $[[T1:[0-9]+]], $7, 32
118 ; 32R6: seleqz $[[T2:[0-9]+]], $[[T0]], $[[T1]]
119 ; 32R6: sra $[[T3:[0-9]+]], $4, 31
120 ; 32R6: selnez $[[T4:[0-9]+]], $[[T3]], $[[T1]]
121 ; 32R6: or $[[T5:[0-9]+]], $[[T4]], $[[T2]]
122 ; 32R6: srlv $[[T6:[0-9]+]], $5, $7
123 ; 32R6: not $[[T7:[0-9]+]], $7
124 ; 32R6: sll $[[T8:[0-9]+]], $4, 1
125 ; 32R6: sllv $[[T9:[0-9]+]], $[[T8]], $[[T7]]
126 ; 32R6: or $[[T10:[0-9]+]], $[[T9]], $[[T6]]
127 ; 32R6: seleqz $[[T11:[0-9]+]], $[[T10]], $[[T1]]
128 ; 32R6: selnez $[[T12:[0-9]+]], $[[T0]], $[[T1]]
129 ; 32R6: jr $ra
130 ; 32R6: or $3, $[[T0]], $[[T11]]
131
132 ; GP64: dsrav $2, $4, $5
133
134 ; MMR3: srlv $[[T0:[0-9]+]], $5, $7
135 ; MMR3: not16 $[[T1:[0-9]+]], $7
136 ; MMR3: sll16 $[[T2:[0-9]+]], $4, 1
137 ; MMR3: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
138 ; MMR3: or16 $[[T4:[0-9]+]], $[[T0]]
139 ; MMR3: srav $[[T5:[0-9]+]], $4, $7
140 ; MMR3: andi16 $[[T6:[0-9]+]], $7, 32
141 ; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]]
142 ; MMR3: sra $[[T8:[0-9]+]], $4, 31
143 ; MMR3: movn $2, $[[T8]], $[[T6]]
144
145 ; MMR6: srav $[[T0:[0-9]+]], $4, $7
146 ; MMR6: andi16 $[[T1:[0-9]+]], $7, 32
147 ; MMR6: seleqz $[[T2:[0-9]+]], $[[T0]], $[[T1]]
148 ; MMR6: sra $[[T3:[0-9]+]], $4, 31
149 ; MMR6: selnez $[[T4:[0-9]+]], $[[T3]], $[[T1]]
150 ; MMR6: or $[[T5:[0-9]+]], $[[T4]], $[[T2]]
151 ; MMR6: srlv $[[T6:[0-9]+]], $5, $7
152 ; MMR6: not16 $[[T7:[0-9]+]], $7
153 ; MMR6: sll16 $[[T8:[0-9]+]], $4, 1
154 ; MMR6: sllv $[[T9:[0-9]+]], $[[T8]], $[[T7]]
155 ; MMR6: or16 $[[T10:[0-9]+]], $[[T6]]
156 ; MMR6: seleqz $[[T11:[0-9]+]], $[[T10]], $[[T1]]
157 ; MMR6: selnez $[[T12:[0-9]+]], $[[T0]], $[[T1]]
158 ; MMR6: or $3, $[[T12]], $[[T11]]
159
160 %r = ashr i64 %a, %b 397 %r = ashr i64 %a, %b
161 ret i64 %r 398 ret i64 %r
162 } 399 }
163 400
164 define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) { 401 define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
402 ; MIPS-LABEL: ashr_i128:
403 ; MIPS: # %bb.0: # %entry
404 ; MIPS-NEXT: addiu $sp, $sp, -8
405 ; MIPS-NEXT: .cfi_def_cfa_offset 8
406 ; MIPS-NEXT: sw $17, 4($sp) # 4-byte Folded Spill
407 ; MIPS-NEXT: sw $16, 0($sp) # 4-byte Folded Spill
408 ; MIPS-NEXT: .cfi_offset 17, -4
409 ; MIPS-NEXT: .cfi_offset 16, -8
410 ; MIPS-NEXT: lw $25, 36($sp)
411 ; MIPS-NEXT: addiu $1, $zero, 64
412 ; MIPS-NEXT: subu $11, $1, $25
413 ; MIPS-NEXT: sllv $9, $5, $11
414 ; MIPS-NEXT: andi $13, $11, 32
415 ; MIPS-NEXT: addiu $2, $zero, 0
416 ; MIPS-NEXT: bnez $13, $BB5_2
417 ; MIPS-NEXT: addiu $3, $zero, 0
418 ; MIPS-NEXT: # %bb.1: # %entry
419 ; MIPS-NEXT: move $3, $9
420 ; MIPS-NEXT: $BB5_2: # %entry
421 ; MIPS-NEXT: not $gp, $25
422 ; MIPS-NEXT: srlv $12, $6, $25
423 ; MIPS-NEXT: andi $8, $25, 32
424 ; MIPS-NEXT: bnez $8, $BB5_4
425 ; MIPS-NEXT: move $15, $12
426 ; MIPS-NEXT: # %bb.3: # %entry
427 ; MIPS-NEXT: srlv $1, $7, $25
428 ; MIPS-NEXT: sll $10, $6, 1
429 ; MIPS-NEXT: sllv $10, $10, $gp
430 ; MIPS-NEXT: or $15, $10, $1
431 ; MIPS-NEXT: $BB5_4: # %entry
432 ; MIPS-NEXT: addiu $10, $25, -64
433 ; MIPS-NEXT: sll $17, $4, 1
434 ; MIPS-NEXT: srav $14, $4, $10
435 ; MIPS-NEXT: andi $24, $10, 32
436 ; MIPS-NEXT: bnez $24, $BB5_6
437 ; MIPS-NEXT: move $16, $14
438 ; MIPS-NEXT: # %bb.5: # %entry
439 ; MIPS-NEXT: srlv $1, $5, $10
440 ; MIPS-NEXT: not $10, $10
441 ; MIPS-NEXT: sllv $10, $17, $10
442 ; MIPS-NEXT: or $16, $10, $1
443 ; MIPS-NEXT: $BB5_6: # %entry
444 ; MIPS-NEXT: sltiu $10, $25, 64
445 ; MIPS-NEXT: beqz $10, $BB5_8
446 ; MIPS-NEXT: nop
447 ; MIPS-NEXT: # %bb.7:
448 ; MIPS-NEXT: or $16, $15, $3
449 ; MIPS-NEXT: $BB5_8: # %entry
450 ; MIPS-NEXT: srav $15, $4, $25
451 ; MIPS-NEXT: beqz $8, $BB5_20
452 ; MIPS-NEXT: move $3, $15
453 ; MIPS-NEXT: # %bb.9: # %entry
454 ; MIPS-NEXT: sltiu $gp, $25, 1
455 ; MIPS-NEXT: beqz $gp, $BB5_21
456 ; MIPS-NEXT: nop
457 ; MIPS-NEXT: $BB5_10: # %entry
458 ; MIPS-NEXT: beqz $10, $BB5_22
459 ; MIPS-NEXT: sra $25, $4, 31
460 ; MIPS-NEXT: $BB5_11: # %entry
461 ; MIPS-NEXT: beqz $13, $BB5_23
462 ; MIPS-NEXT: nop
463 ; MIPS-NEXT: $BB5_12: # %entry
464 ; MIPS-NEXT: beqz $8, $BB5_24
465 ; MIPS-NEXT: nop
466 ; MIPS-NEXT: $BB5_13: # %entry
467 ; MIPS-NEXT: beqz $24, $BB5_25
468 ; MIPS-NEXT: move $4, $25
469 ; MIPS-NEXT: $BB5_14: # %entry
470 ; MIPS-NEXT: bnez $10, $BB5_26
471 ; MIPS-NEXT: nop
472 ; MIPS-NEXT: $BB5_15: # %entry
473 ; MIPS-NEXT: beqz $gp, $BB5_27
474 ; MIPS-NEXT: nop
475 ; MIPS-NEXT: $BB5_16: # %entry
476 ; MIPS-NEXT: beqz $8, $BB5_28
477 ; MIPS-NEXT: move $2, $25
478 ; MIPS-NEXT: $BB5_17: # %entry
479 ; MIPS-NEXT: bnez $10, $BB5_19
480 ; MIPS-NEXT: nop
481 ; MIPS-NEXT: $BB5_18: # %entry
482 ; MIPS-NEXT: move $2, $25
483 ; MIPS-NEXT: $BB5_19: # %entry
484 ; MIPS-NEXT: move $4, $6
485 ; MIPS-NEXT: move $5, $7
486 ; MIPS-NEXT: lw $16, 0($sp) # 4-byte Folded Reload
487 ; MIPS-NEXT: lw $17, 4($sp) # 4-byte Folded Reload
488 ; MIPS-NEXT: jr $ra
489 ; MIPS-NEXT: addiu $sp, $sp, 8
490 ; MIPS-NEXT: $BB5_20: # %entry
491 ; MIPS-NEXT: srlv $1, $5, $25
492 ; MIPS-NEXT: sllv $3, $17, $gp
493 ; MIPS-NEXT: sltiu $gp, $25, 1
494 ; MIPS-NEXT: bnez $gp, $BB5_10
495 ; MIPS-NEXT: or $3, $3, $1
496 ; MIPS-NEXT: $BB5_21: # %entry
497 ; MIPS-NEXT: move $7, $16
498 ; MIPS-NEXT: bnez $10, $BB5_11
499 ; MIPS-NEXT: sra $25, $4, 31
500 ; MIPS-NEXT: $BB5_22: # %entry
501 ; MIPS-NEXT: bnez $13, $BB5_12
502 ; MIPS-NEXT: move $3, $25
503 ; MIPS-NEXT: $BB5_23: # %entry
504 ; MIPS-NEXT: not $1, $11
505 ; MIPS-NEXT: srl $5, $5, 1
506 ; MIPS-NEXT: sllv $4, $4, $11
507 ; MIPS-NEXT: srlv $1, $5, $1
508 ; MIPS-NEXT: bnez $8, $BB5_13
509 ; MIPS-NEXT: or $9, $4, $1
510 ; MIPS-NEXT: $BB5_24: # %entry
511 ; MIPS-NEXT: move $2, $12
512 ; MIPS-NEXT: bnez $24, $BB5_14
513 ; MIPS-NEXT: move $4, $25
514 ; MIPS-NEXT: $BB5_25: # %entry
515 ; MIPS-NEXT: beqz $10, $BB5_15
516 ; MIPS-NEXT: move $4, $14
517 ; MIPS-NEXT: $BB5_26:
518 ; MIPS-NEXT: bnez $gp, $BB5_16
519 ; MIPS-NEXT: or $4, $2, $9
520 ; MIPS-NEXT: $BB5_27: # %entry
521 ; MIPS-NEXT: move $6, $4
522 ; MIPS-NEXT: bnez $8, $BB5_17
523 ; MIPS-NEXT: move $2, $25
524 ; MIPS-NEXT: $BB5_28: # %entry
525 ; MIPS-NEXT: bnez $10, $BB5_19
526 ; MIPS-NEXT: move $2, $15
527 ; MIPS-NEXT: # %bb.29: # %entry
528 ; MIPS-NEXT: b $BB5_18
529 ; MIPS-NEXT: nop
530 ;
531 ; MIPS32-LABEL: ashr_i128:
532 ; MIPS32: # %bb.0: # %entry
533 ; MIPS32-NEXT: lw $9, 28($sp)
534 ; MIPS32-NEXT: srlv $1, $7, $9
535 ; MIPS32-NEXT: not $2, $9
536 ; MIPS32-NEXT: sll $3, $6, 1
537 ; MIPS32-NEXT: sllv $3, $3, $2
538 ; MIPS32-NEXT: addiu $8, $zero, 64
539 ; MIPS32-NEXT: or $1, $3, $1
540 ; MIPS32-NEXT: srlv $10, $6, $9
541 ; MIPS32-NEXT: subu $3, $8, $9
542 ; MIPS32-NEXT: sllv $11, $5, $3
543 ; MIPS32-NEXT: andi $12, $3, 32
544 ; MIPS32-NEXT: andi $13, $9, 32
545 ; MIPS32-NEXT: move $8, $11
546 ; MIPS32-NEXT: movn $8, $zero, $12
547 ; MIPS32-NEXT: movn $1, $10, $13
548 ; MIPS32-NEXT: addiu $14, $9, -64
549 ; MIPS32-NEXT: srlv $15, $5, $14
550 ; MIPS32-NEXT: sll $24, $4, 1
551 ; MIPS32-NEXT: not $25, $14
552 ; MIPS32-NEXT: sllv $25, $24, $25
553 ; MIPS32-NEXT: or $gp, $1, $8
554 ; MIPS32-NEXT: or $1, $25, $15
555 ; MIPS32-NEXT: srav $8, $4, $14
556 ; MIPS32-NEXT: andi $14, $14, 32
557 ; MIPS32-NEXT: movn $1, $8, $14
558 ; MIPS32-NEXT: sllv $15, $4, $3
559 ; MIPS32-NEXT: not $3, $3
560 ; MIPS32-NEXT: srl $25, $5, 1
561 ; MIPS32-NEXT: srlv $3, $25, $3
562 ; MIPS32-NEXT: sltiu $25, $9, 64
563 ; MIPS32-NEXT: movn $1, $gp, $25
564 ; MIPS32-NEXT: or $15, $15, $3
565 ; MIPS32-NEXT: srlv $3, $5, $9
566 ; MIPS32-NEXT: sllv $2, $24, $2
567 ; MIPS32-NEXT: or $5, $2, $3
568 ; MIPS32-NEXT: srav $24, $4, $9
569 ; MIPS32-NEXT: movn $5, $24, $13
570 ; MIPS32-NEXT: sra $2, $4, 31
571 ; MIPS32-NEXT: movz $1, $7, $9
572 ; MIPS32-NEXT: move $3, $2
573 ; MIPS32-NEXT: movn $3, $5, $25
574 ; MIPS32-NEXT: movn $15, $11, $12
575 ; MIPS32-NEXT: movn $10, $zero, $13
576 ; MIPS32-NEXT: or $4, $10, $15
577 ; MIPS32-NEXT: movn $8, $2, $14
578 ; MIPS32-NEXT: movn $8, $4, $25
579 ; MIPS32-NEXT: movz $8, $6, $9
580 ; MIPS32-NEXT: movn $24, $2, $13
581 ; MIPS32-NEXT: movn $2, $24, $25
582 ; MIPS32-NEXT: move $4, $8
583 ; MIPS32-NEXT: jr $ra
584 ; MIPS32-NEXT: move $5, $1
585 ;
586 ; 32R2-LABEL: ashr_i128:
587 ; 32R2: # %bb.0: # %entry
588 ; 32R2-NEXT: lw $9, 28($sp)
589 ; 32R2-NEXT: srlv $1, $7, $9
590 ; 32R2-NEXT: not $2, $9
591 ; 32R2-NEXT: sll $3, $6, 1
592 ; 32R2-NEXT: sllv $3, $3, $2
593 ; 32R2-NEXT: addiu $8, $zero, 64
594 ; 32R2-NEXT: or $1, $3, $1
595 ; 32R2-NEXT: srlv $10, $6, $9
596 ; 32R2-NEXT: subu $3, $8, $9
597 ; 32R2-NEXT: sllv $11, $5, $3
598 ; 32R2-NEXT: andi $12, $3, 32
599 ; 32R2-NEXT: andi $13, $9, 32
600 ; 32R2-NEXT: move $8, $11
601 ; 32R2-NEXT: movn $8, $zero, $12
602 ; 32R2-NEXT: movn $1, $10, $13
603 ; 32R2-NEXT: addiu $14, $9, -64
604 ; 32R2-NEXT: srlv $15, $5, $14
605 ; 32R2-NEXT: sll $24, $4, 1
606 ; 32R2-NEXT: not $25, $14
607 ; 32R2-NEXT: sllv $25, $24, $25
608 ; 32R2-NEXT: or $gp, $1, $8
609 ; 32R2-NEXT: or $1, $25, $15
610 ; 32R2-NEXT: srav $8, $4, $14
611 ; 32R2-NEXT: andi $14, $14, 32
612 ; 32R2-NEXT: movn $1, $8, $14
613 ; 32R2-NEXT: sllv $15, $4, $3
614 ; 32R2-NEXT: not $3, $3
615 ; 32R2-NEXT: srl $25, $5, 1
616 ; 32R2-NEXT: srlv $3, $25, $3
617 ; 32R2-NEXT: sltiu $25, $9, 64
618 ; 32R2-NEXT: movn $1, $gp, $25
619 ; 32R2-NEXT: or $15, $15, $3
620 ; 32R2-NEXT: srlv $3, $5, $9
621 ; 32R2-NEXT: sllv $2, $24, $2
622 ; 32R2-NEXT: or $5, $2, $3
623 ; 32R2-NEXT: srav $24, $4, $9
624 ; 32R2-NEXT: movn $5, $24, $13
625 ; 32R2-NEXT: sra $2, $4, 31
626 ; 32R2-NEXT: movz $1, $7, $9
627 ; 32R2-NEXT: move $3, $2
628 ; 32R2-NEXT: movn $3, $5, $25
629 ; 32R2-NEXT: movn $15, $11, $12
630 ; 32R2-NEXT: movn $10, $zero, $13
631 ; 32R2-NEXT: or $4, $10, $15
632 ; 32R2-NEXT: movn $8, $2, $14
633 ; 32R2-NEXT: movn $8, $4, $25
634 ; 32R2-NEXT: movz $8, $6, $9
635 ; 32R2-NEXT: movn $24, $2, $13
636 ; 32R2-NEXT: movn $2, $24, $25
637 ; 32R2-NEXT: move $4, $8
638 ; 32R2-NEXT: jr $ra
639 ; 32R2-NEXT: move $5, $1
640 ;
641 ; 32R6-LABEL: ashr_i128:
642 ; 32R6: # %bb.0: # %entry
643 ; 32R6-NEXT: lw $3, 28($sp)
644 ; 32R6-NEXT: addiu $1, $zero, 64
645 ; 32R6-NEXT: subu $1, $1, $3
646 ; 32R6-NEXT: sllv $2, $5, $1
647 ; 32R6-NEXT: andi $8, $1, 32
648 ; 32R6-NEXT: selnez $9, $2, $8
649 ; 32R6-NEXT: sllv $10, $4, $1
650 ; 32R6-NEXT: not $1, $1
651 ; 32R6-NEXT: srl $11, $5, 1
652 ; 32R6-NEXT: srlv $1, $11, $1
653 ; 32R6-NEXT: or $1, $10, $1
654 ; 32R6-NEXT: seleqz $1, $1, $8
655 ; 32R6-NEXT: or $1, $9, $1
656 ; 32R6-NEXT: srlv $9, $7, $3
657 ; 32R6-NEXT: not $10, $3
658 ; 32R6-NEXT: sll $11, $6, 1
659 ; 32R6-NEXT: sllv $11, $11, $10
660 ; 32R6-NEXT: or $9, $11, $9
661 ; 32R6-NEXT: andi $11, $3, 32
662 ; 32R6-NEXT: seleqz $9, $9, $11
663 ; 32R6-NEXT: srlv $12, $6, $3
664 ; 32R6-NEXT: selnez $13, $12, $11
665 ; 32R6-NEXT: seleqz $12, $12, $11
666 ; 32R6-NEXT: or $1, $12, $1
667 ; 32R6-NEXT: seleqz $2, $2, $8
668 ; 32R6-NEXT: or $8, $13, $9
669 ; 32R6-NEXT: addiu $9, $3, -64
670 ; 32R6-NEXT: srlv $12, $5, $9
671 ; 32R6-NEXT: sll $13, $4, 1
672 ; 32R6-NEXT: not $14, $9
673 ; 32R6-NEXT: sllv $14, $13, $14
674 ; 32R6-NEXT: sltiu $15, $3, 64
675 ; 32R6-NEXT: or $2, $8, $2
676 ; 32R6-NEXT: selnez $1, $1, $15
677 ; 32R6-NEXT: or $8, $14, $12
678 ; 32R6-NEXT: srav $12, $4, $9
679 ; 32R6-NEXT: andi $9, $9, 32
680 ; 32R6-NEXT: seleqz $14, $12, $9
681 ; 32R6-NEXT: sra $24, $4, 31
682 ; 32R6-NEXT: selnez $25, $24, $9
683 ; 32R6-NEXT: seleqz $8, $8, $9
684 ; 32R6-NEXT: or $14, $25, $14
685 ; 32R6-NEXT: seleqz $14, $14, $15
686 ; 32R6-NEXT: selnez $9, $12, $9
687 ; 32R6-NEXT: seleqz $12, $24, $15
688 ; 32R6-NEXT: or $1, $1, $14
689 ; 32R6-NEXT: selnez $14, $1, $3
690 ; 32R6-NEXT: selnez $1, $2, $15
691 ; 32R6-NEXT: or $2, $9, $8
692 ; 32R6-NEXT: srav $8, $4, $3
693 ; 32R6-NEXT: seleqz $4, $8, $11
694 ; 32R6-NEXT: selnez $9, $24, $11
695 ; 32R6-NEXT: or $4, $9, $4
696 ; 32R6-NEXT: selnez $9, $4, $15
697 ; 32R6-NEXT: seleqz $2, $2, $15
698 ; 32R6-NEXT: seleqz $4, $6, $3
699 ; 32R6-NEXT: seleqz $6, $7, $3
700 ; 32R6-NEXT: or $1, $1, $2
701 ; 32R6-NEXT: selnez $1, $1, $3
702 ; 32R6-NEXT: or $1, $6, $1
703 ; 32R6-NEXT: or $4, $4, $14
704 ; 32R6-NEXT: or $2, $9, $12
705 ; 32R6-NEXT: srlv $3, $5, $3
706 ; 32R6-NEXT: sllv $5, $13, $10
707 ; 32R6-NEXT: or $3, $5, $3
708 ; 32R6-NEXT: seleqz $3, $3, $11
709 ; 32R6-NEXT: selnez $5, $8, $11
710 ; 32R6-NEXT: or $3, $5, $3
711 ; 32R6-NEXT: selnez $3, $3, $15
712 ; 32R6-NEXT: or $3, $3, $12
713 ; 32R6-NEXT: jr $ra
714 ; 32R6-NEXT: move $5, $1
715 ;
716 ; MIPS3-LABEL: ashr_i128:
717 ; MIPS3: # %bb.0: # %entry
718 ; MIPS3-NEXT: sll $8, $7, 0
719 ; MIPS3-NEXT: dsrav $2, $4, $7
720 ; MIPS3-NEXT: andi $6, $8, 64
721 ; MIPS3-NEXT: beqz $6, .LBB5_3
722 ; MIPS3-NEXT: move $3, $2
723 ; MIPS3-NEXT: # %bb.1: # %entry
724 ; MIPS3-NEXT: bnez $6, .LBB5_4
725 ; MIPS3-NEXT: nop
726 ; MIPS3-NEXT: .LBB5_2: # %entry
727 ; MIPS3-NEXT: jr $ra
728 ; MIPS3-NEXT: nop
729 ; MIPS3-NEXT: .LBB5_3: # %entry
730 ; MIPS3-NEXT: dsrlv $1, $5, $7
731 ; MIPS3-NEXT: dsll $3, $4, 1
732 ; MIPS3-NEXT: not $5, $8
733 ; MIPS3-NEXT: dsllv $3, $3, $5
734 ; MIPS3-NEXT: beqz $6, .LBB5_2
735 ; MIPS3-NEXT: or $3, $3, $1
736 ; MIPS3-NEXT: .LBB5_4:
737 ; MIPS3-NEXT: jr $ra
738 ; MIPS3-NEXT: dsra $2, $4, 63
739 ;
740 ; MIPS64-LABEL: ashr_i128:
741 ; MIPS64: # %bb.0: # %entry
742 ; MIPS64-NEXT: dsrlv $1, $5, $7
743 ; MIPS64-NEXT: dsll $2, $4, 1
744 ; MIPS64-NEXT: sll $5, $7, 0
745 ; MIPS64-NEXT: not $3, $5
746 ; MIPS64-NEXT: dsllv $2, $2, $3
747 ; MIPS64-NEXT: or $3, $2, $1
748 ; MIPS64-NEXT: dsrav $2, $4, $7
749 ; MIPS64-NEXT: andi $1, $5, 64
750 ; MIPS64-NEXT: movn $3, $2, $1
751 ; MIPS64-NEXT: dsra $4, $4, 63
752 ; MIPS64-NEXT: jr $ra
753 ; MIPS64-NEXT: movn $2, $4, $1
754 ;
755 ; MIPS64R2-LABEL: ashr_i128:
756 ; MIPS64R2: # %bb.0: # %entry
757 ; MIPS64R2-NEXT: dsrlv $1, $5, $7
758 ; MIPS64R2-NEXT: dsll $2, $4, 1
759 ; MIPS64R2-NEXT: sll $5, $7, 0
760 ; MIPS64R2-NEXT: not $3, $5
761 ; MIPS64R2-NEXT: dsllv $2, $2, $3
762 ; MIPS64R2-NEXT: or $3, $2, $1
763 ; MIPS64R2-NEXT: dsrav $2, $4, $7
764 ; MIPS64R2-NEXT: andi $1, $5, 64
765 ; MIPS64R2-NEXT: movn $3, $2, $1
766 ; MIPS64R2-NEXT: dsra $4, $4, 63
767 ; MIPS64R2-NEXT: jr $ra
768 ; MIPS64R2-NEXT: movn $2, $4, $1
769 ;
770 ; MIPS64R6-LABEL: ashr_i128:
771 ; MIPS64R6: # %bb.0: # %entry
772 ; MIPS64R6-NEXT: dsrav $1, $4, $7
773 ; MIPS64R6-NEXT: sll $3, $7, 0
774 ; MIPS64R6-NEXT: andi $2, $3, 64
775 ; MIPS64R6-NEXT: sll $6, $2, 0
776 ; MIPS64R6-NEXT: seleqz $2, $1, $6
777 ; MIPS64R6-NEXT: dsra $8, $4, 63
778 ; MIPS64R6-NEXT: selnez $8, $8, $6
779 ; MIPS64R6-NEXT: or $2, $8, $2
780 ; MIPS64R6-NEXT: dsrlv $5, $5, $7
781 ; MIPS64R6-NEXT: dsll $4, $4, 1
782 ; MIPS64R6-NEXT: not $3, $3
783 ; MIPS64R6-NEXT: dsllv $3, $4, $3
784 ; MIPS64R6-NEXT: or $3, $3, $5
785 ; MIPS64R6-NEXT: seleqz $3, $3, $6
786 ; MIPS64R6-NEXT: selnez $1, $1, $6
787 ; MIPS64R6-NEXT: jr $ra
788 ; MIPS64R6-NEXT: or $3, $1, $3
789 ;
790 ; MMR3-LABEL: ashr_i128:
791 ; MMR3: # %bb.0: # %entry
792 ; MMR3-NEXT: addiusp -48
793 ; MMR3-NEXT: .cfi_def_cfa_offset 48
794 ; MMR3-NEXT: sw $17, 44($sp) # 4-byte Folded Spill
795 ; MMR3-NEXT: sw $16, 40($sp) # 4-byte Folded Spill
796 ; MMR3-NEXT: .cfi_offset 17, -4
797 ; MMR3-NEXT: .cfi_offset 16, -8
798 ; MMR3-NEXT: move $8, $7
799 ; MMR3-NEXT: sw $6, 32($sp) # 4-byte Folded Spill
800 ; MMR3-NEXT: sw $5, 36($sp) # 4-byte Folded Spill
801 ; MMR3-NEXT: sw $4, 8($sp) # 4-byte Folded Spill
802 ; MMR3-NEXT: lw $16, 76($sp)
803 ; MMR3-NEXT: srlv $4, $7, $16
804 ; MMR3-NEXT: not16 $3, $16
805 ; MMR3-NEXT: sw $3, 24($sp) # 4-byte Folded Spill
806 ; MMR3-NEXT: sll16 $2, $6, 1
807 ; MMR3-NEXT: sllv $3, $2, $3
808 ; MMR3-NEXT: li16 $2, 64
809 ; MMR3-NEXT: or16 $3, $4
810 ; MMR3-NEXT: srlv $6, $6, $16
811 ; MMR3-NEXT: sw $6, 12($sp) # 4-byte Folded Spill
812 ; MMR3-NEXT: subu16 $7, $2, $16
813 ; MMR3-NEXT: sllv $9, $5, $7
814 ; MMR3-NEXT: andi16 $2, $7, 32
815 ; MMR3-NEXT: sw $2, 28($sp) # 4-byte Folded Spill
816 ; MMR3-NEXT: andi16 $5, $16, 32
817 ; MMR3-NEXT: sw $5, 16($sp) # 4-byte Folded Spill
818 ; MMR3-NEXT: move $4, $9
819 ; MMR3-NEXT: li16 $17, 0
820 ; MMR3-NEXT: movn $4, $17, $2
821 ; MMR3-NEXT: movn $3, $6, $5
822 ; MMR3-NEXT: addiu $2, $16, -64
823 ; MMR3-NEXT: lw $5, 36($sp) # 4-byte Folded Reload
824 ; MMR3-NEXT: srlv $5, $5, $2
825 ; MMR3-NEXT: sw $5, 20($sp) # 4-byte Folded Spill
826 ; MMR3-NEXT: lw $17, 8($sp) # 4-byte Folded Reload
827 ; MMR3-NEXT: sll16 $6, $17, 1
828 ; MMR3-NEXT: sw $6, 4($sp) # 4-byte Folded Spill
829 ; MMR3-NEXT: not16 $5, $2
830 ; MMR3-NEXT: sllv $5, $6, $5
831 ; MMR3-NEXT: or16 $3, $4
832 ; MMR3-NEXT: lw $4, 20($sp) # 4-byte Folded Reload
833 ; MMR3-NEXT: or16 $5, $4
834 ; MMR3-NEXT: srav $1, $17, $2
835 ; MMR3-NEXT: andi16 $2, $2, 32
836 ; MMR3-NEXT: sw $2, 20($sp) # 4-byte Folded Spill
837 ; MMR3-NEXT: movn $5, $1, $2
838 ; MMR3-NEXT: sllv $2, $17, $7
839 ; MMR3-NEXT: not16 $4, $7
840 ; MMR3-NEXT: lw $7, 36($sp) # 4-byte Folded Reload
841 ; MMR3-NEXT: srl16 $6, $7, 1
842 ; MMR3-NEXT: srlv $6, $6, $4
843 ; MMR3-NEXT: sltiu $10, $16, 64
844 ; MMR3-NEXT: movn $5, $3, $10
845 ; MMR3-NEXT: or16 $6, $2
846 ; MMR3-NEXT: srlv $2, $7, $16
847 ; MMR3-NEXT: lw $3, 24($sp) # 4-byte Folded Reload
848 ; MMR3-NEXT: lw $4, 4($sp) # 4-byte Folded Reload
849 ; MMR3-NEXT: sllv $3, $4, $3
850 ; MMR3-NEXT: or16 $3, $2
851 ; MMR3-NEXT: srav $11, $17, $16
852 ; MMR3-NEXT: lw $4, 16($sp) # 4-byte Folded Reload
853 ; MMR3-NEXT: movn $3, $11, $4
854 ; MMR3-NEXT: sra $2, $17, 31
855 ; MMR3-NEXT: movz $5, $8, $16
856 ; MMR3-NEXT: move $8, $2
857 ; MMR3-NEXT: movn $8, $3, $10
858 ; MMR3-NEXT: lw $3, 28($sp) # 4-byte Folded Reload
859 ; MMR3-NEXT: movn $6, $9, $3
860 ; MMR3-NEXT: li16 $3, 0
861 ; MMR3-NEXT: lw $7, 12($sp) # 4-byte Folded Reload
862 ; MMR3-NEXT: movn $7, $3, $4
863 ; MMR3-NEXT: or16 $7, $6
864 ; MMR3-NEXT: lw $3, 20($sp) # 4-byte Folded Reload
865 ; MMR3-NEXT: movn $1, $2, $3
866 ; MMR3-NEXT: movn $1, $7, $10
867 ; MMR3-NEXT: lw $3, 32($sp) # 4-byte Folded Reload
868 ; MMR3-NEXT: movz $1, $3, $16
869 ; MMR3-NEXT: movn $11, $2, $4
870 ; MMR3-NEXT: movn $2, $11, $10
871 ; MMR3-NEXT: move $3, $8
872 ; MMR3-NEXT: move $4, $1
873 ; MMR3-NEXT: lw $16, 40($sp) # 4-byte Folded Reload
874 ; MMR3-NEXT: lw $17, 44($sp) # 4-byte Folded Reload
875 ; MMR3-NEXT: addiusp 48
876 ; MMR3-NEXT: jrc $ra
877 ;
878 ; MMR6-LABEL: ashr_i128:
879 ; MMR6: # %bb.0: # %entry
880 ; MMR6-NEXT: addiu $sp, $sp, -16
881 ; MMR6-NEXT: .cfi_def_cfa_offset 16
882 ; MMR6-NEXT: sw $17, 12($sp) # 4-byte Folded Spill
883 ; MMR6-NEXT: sw $16, 8($sp) # 4-byte Folded Spill
884 ; MMR6-NEXT: .cfi_offset 17, -4
885 ; MMR6-NEXT: .cfi_offset 16, -8
886 ; MMR6-NEXT: move $1, $7
887 ; MMR6-NEXT: lw $3, 44($sp)
888 ; MMR6-NEXT: li16 $2, 64
889 ; MMR6-NEXT: subu16 $7, $2, $3
890 ; MMR6-NEXT: sllv $8, $5, $7
891 ; MMR6-NEXT: andi16 $2, $7, 32
892 ; MMR6-NEXT: selnez $9, $8, $2
893 ; MMR6-NEXT: sllv $10, $4, $7
894 ; MMR6-NEXT: not16 $7, $7
895 ; MMR6-NEXT: srl16 $16, $5, 1
896 ; MMR6-NEXT: srlv $7, $16, $7
897 ; MMR6-NEXT: or $7, $10, $7
898 ; MMR6-NEXT: seleqz $7, $7, $2
899 ; MMR6-NEXT: or $7, $9, $7
900 ; MMR6-NEXT: srlv $9, $1, $3
901 ; MMR6-NEXT: not16 $16, $3
902 ; MMR6-NEXT: sw $16, 4($sp) # 4-byte Folded Spill
903 ; MMR6-NEXT: sll16 $17, $6, 1
904 ; MMR6-NEXT: sllv $10, $17, $16
905 ; MMR6-NEXT: or $9, $10, $9
906 ; MMR6-NEXT: andi16 $17, $3, 32
907 ; MMR6-NEXT: seleqz $9, $9, $17
908 ; MMR6-NEXT: srlv $10, $6, $3
909 ; MMR6-NEXT: selnez $11, $10, $17
910 ; MMR6-NEXT: seleqz $10, $10, $17
911 ; MMR6-NEXT: or $10, $10, $7
912 ; MMR6-NEXT: seleqz $12, $8, $2
913 ; MMR6-NEXT: or $8, $11, $9
914 ; MMR6-NEXT: addiu $2, $3, -64
915 ; MMR6-NEXT: srlv $9, $5, $2
916 ; MMR6-NEXT: sll16 $7, $4, 1
917 ; MMR6-NEXT: not16 $16, $2
918 ; MMR6-NEXT: sllv $11, $7, $16
919 ; MMR6-NEXT: sltiu $13, $3, 64
920 ; MMR6-NEXT: or $8, $8, $12
921 ; MMR6-NEXT: selnez $10, $10, $13
922 ; MMR6-NEXT: or $9, $11, $9
923 ; MMR6-NEXT: srav $11, $4, $2
924 ; MMR6-NEXT: andi16 $2, $2, 32
925 ; MMR6-NEXT: seleqz $12, $11, $2
926 ; MMR6-NEXT: sra $14, $4, 31
927 ; MMR6-NEXT: selnez $15, $14, $2
928 ; MMR6-NEXT: seleqz $9, $9, $2
929 ; MMR6-NEXT: or $12, $15, $12
930 ; MMR6-NEXT: seleqz $12, $12, $13
931 ; MMR6-NEXT: selnez $2, $11, $2
932 ; MMR6-NEXT: seleqz $11, $14, $13
933 ; MMR6-NEXT: or $10, $10, $12
934 ; MMR6-NEXT: selnez $10, $10, $3
935 ; MMR6-NEXT: selnez $8, $8, $13
936 ; MMR6-NEXT: or $2, $2, $9
937 ; MMR6-NEXT: srav $9, $4, $3
938 ; MMR6-NEXT: seleqz $4, $9, $17
939 ; MMR6-NEXT: selnez $12, $14, $17
940 ; MMR6-NEXT: or $4, $12, $4
941 ; MMR6-NEXT: selnez $12, $4, $13
942 ; MMR6-NEXT: seleqz $2, $2, $13
943 ; MMR6-NEXT: seleqz $4, $6, $3
944 ; MMR6-NEXT: seleqz $1, $1, $3
945 ; MMR6-NEXT: or $2, $8, $2
946 ; MMR6-NEXT: selnez $2, $2, $3
947 ; MMR6-NEXT: or $1, $1, $2
948 ; MMR6-NEXT: or $4, $4, $10
949 ; MMR6-NEXT: or $2, $12, $11
950 ; MMR6-NEXT: srlv $3, $5, $3
951 ; MMR6-NEXT: lw $5, 4($sp) # 4-byte Folded Reload
952 ; MMR6-NEXT: sllv $5, $7, $5
953 ; MMR6-NEXT: or $3, $5, $3
954 ; MMR6-NEXT: seleqz $3, $3, $17
955 ; MMR6-NEXT: selnez $5, $9, $17
956 ; MMR6-NEXT: or $3, $5, $3
957 ; MMR6-NEXT: selnez $3, $3, $13
958 ; MMR6-NEXT: or $3, $3, $11
959 ; MMR6-NEXT: move $5, $1
960 ; MMR6-NEXT: lw $16, 8($sp) # 4-byte Folded Reload
961 ; MMR6-NEXT: lw $17, 12($sp) # 4-byte Folded Reload
962 ; MMR6-NEXT: addiu $sp, $sp, 16
963 ; MMR6-NEXT: jrc $ra
165 entry: 964 entry:
166 ; ALL-LABEL: ashr_i128: 965 ; o32 shouldn't use TImode helpers.
167 966 ; GP32-NOT: lw $25, %call16(__ashrti3)($gp)
168 ; o32 shouldn't use TImode helpers. 967 ; MM-NOT: lw $25, %call16(__ashrti3)($2)
169 ; GP32-NOT: lw $25, %call16(__ashrti3)($gp)
170 ; MM-NOT: lw $25, %call16(__ashrti3)($2)
171
172 ; M3: sll $[[T0:[0-9]+]], $7, 0
173 ; M3: dsrav $[[T1:[0-9]+]], $4, $7
174 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
175 ; M3: beqz $[[T3:[0-9]+]], [[BB0:.LBB[0-9_]+]]
176 ; M3: move $3, $[[T1]]
177 ; M3: bnez $[[T3]], [[BB1:.LBB[0-9_]+]]
178 ; M3: nop
179 ; M3: [[EXIT:.LBB[0-9_]+]]:
180 ; M3: jr $ra
181 ; M3: nop
182 ; M3: [[BB0]]:
183 ; M3: dsrlv $[[T4:[0-9]+]], $5, $7
184 ; M3: dsll $[[T5:[0-9]+]], $4, 1
185 ; M3: not $[[T6:[0-9]+]], $[[T0]]
186 ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
187 ; M3: beqz $[[T3]], [[EXIT]]
188 ; M3: or $3, $[[T7]], $[[T4]]
189 ; M3: [[BB1]]:
190 ; M3: jr $ra
191 ; M3: dsra $2, $4, 63
192
193 ; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7
194 ; GP64-NOT-R6: dsll $[[T1:[0-9]+]], $4, 1
195 ; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0
196 ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]]
197 ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
198 ; GP64-NOT-R6: or $3, $[[T4]], $[[T0]]
199 ; GP64-NOT-R6: dsrav $2, $4, $7
200 ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 64
201 ; GP64-NOT-R6: movn $3, $2, $[[T5]]
202 ; GP64-NOT-R6: dsra $[[T6:[0-9]+]], $4, 63
203 ; GP64-NOT-R6: jr $ra
204 ; GP64-NOT-R6: movn $2, $[[T6]], $[[T5]]
205
206 ; 64R6: dsrav $[[T0:[0-9]+]], $4, $7
207 ; 64R6: sll $[[T1:[0-9]+]], $7, 0
208 ; 64R6: andi $[[T2:[0-9]+]], $[[T1]], 64
209 ; 64R6: sll $[[T3:[0-9]+]], $[[T2]], 0
210 ; 64R6: seleqz $[[T4:[0-9]+]], $[[T0]], $[[T3]]
211 ; 64R6: dsra $[[T5:[0-9]+]], $4, 63
212 ; 64R6: selnez $[[T6:[0-9]+]], $[[T5]], $[[T3]]
213 ; 64R6: or $2, $[[T6]], $[[T4]]
214 ; 64R6: dsrlv $[[T7:[0-9]+]], $5, $7
215 ; 64R6: dsll $[[T8:[0-9]+]], $4, 1
216 ; 64R6: not $[[T9:[0-9]+]], $[[T1]]
217 ; 64R6: dsllv $[[T10:[0-9]+]], $[[T8]], $[[T9]]
218 ; 64R6: or $[[T11:[0-9]+]], $[[T10]], $[[T7]]
219 ; 64R6: seleqz $[[T12:[0-9]+]], $[[T11]], $[[T3]]
220 ; 64R6: selnez $[[T13:[0-9]+]], $[[T0]], $[[T3]]
221 ; 64R6: jr $ra
222 ; 64R6: or $3, $[[T13]], $[[T12]]
223 968
224 %r = ashr i128 %a, %b 969 %r = ashr i128 %a, %b
225 ret i128 %r 970 ret i128 %r
226 } 971 }