CbC/CbC_llvm: lib/CodeGen/TailDuplication.cpp comparison

comparison lib/CodeGen/TailDuplication.cpp @ 77:54457678186b LLVM3.6

LLVM 3.6

author	Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date	Mon, 08 Sep 2014 22:06:00 +0900
parents	95c75e76d11b
children	60c9769439b8

comparison

equal deleted inserted replaced

-:e874dbf0ad9d
+:54457678186b
 // This pass duplicates basic blocks ending in unconditional branches into
 // the tails of their predecessors.
 //
 //===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "tailduplication"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/ADT/DenseSet.h"
-#include "llvm/ADT/OwningPtr.h"
 #include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/MachineSSAUpdater.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
 using namespace llvm;
+#define DEBUG_TYPE "tailduplication"
 STATISTIC(NumTails     , "Number of tails duplicated");
 STATISTIC(NumTailDups  , "Number of tail duplicated blocks");
 STATISTIC(NumInstrDups , "Additional instructions due to tail duplication");
 STATISTIC(NumDeadBlocks, "Number of dead blocks removed");
 namespace {
 /// TailDuplicatePass - Perform tail duplication.
 class TailDuplicatePass : public MachineFunctionPass {
 const TargetInstrInfo *TII;
 const TargetRegisterInfo *TRI;
+const MachineBranchProbabilityInfo *MBPI;
 MachineModuleInfo *MMI;
 MachineRegisterInfo *MRI;
-OwningPtr<RegScavenger> RS;
+std::unique_ptr<RegScavenger> RS;
 bool PreRegAlloc;
 // SSAUpdateVRs - A list of virtual registers for which to update SSA form.
 SmallVector<unsigned, 16> SSAUpdateVRs;
 public:
 static char ID;
 explicit TailDuplicatePass() :
 MachineFunctionPass(ID), PreRegAlloc(false) {}
-virtual bool runOnMachineFunction(MachineFunction &MF);
+bool runOnMachineFunction(MachineFunction &MF) override;
+void getAnalysisUsage(AnalysisUsage &AU) const override;
 private:
 void AddSSAUpdateEntry(unsigned OrigReg, unsigned NewReg,
 MachineBasicBlock *BB);
 void ProcessPHI(MachineInstr *MI, MachineBasicBlock *TailBB,
 INITIALIZE_PASS(TailDuplicatePass, "tailduplication", "Tail Duplication",
 false, false)
 bool TailDuplicatePass::runOnMachineFunction(MachineFunction &MF) {
-TII = MF.getTarget().getInstrInfo();
+if (skipOptnoneFunction(*MF.getFunction()))
-TRI = MF.getTarget().getRegisterInfo();
+return false;
+TII = MF.getSubtarget().getInstrInfo();
+TRI = MF.getSubtarget().getRegisterInfo();
 MRI = &MF.getRegInfo();
 MMI = getAnalysisIfAvailable<MachineModuleInfo>();
+MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
 PreRegAlloc = MRI->isSSA();
 RS.reset();
 if (MRI->tracksLiveness() && TRI->trackLivenessAfterRegAlloc(MF))
 RS.reset(new RegScavenger());
 bool MadeChange = false;
 while (TailDuplicateBlocks(MF))
 MadeChange = true;
 return MadeChange;
+}
+void TailDuplicatePass::getAnalysisUsage(AnalysisUsage &AU) const {
+AU.addRequired<MachineBranchProbabilityInfo>();
+MachineFunctionPass::getAnalysisUsage(AU);
 }
 static void VerifyPHIs(MachineFunction &MF, bool CheckExtra) {
 for (MachineFunction::iterator I = ++MF.begin(), E = MF.end(); I != E; ++I) {
 MachineBasicBlock *MBB = I;
 }
 if (!Found) {
 dbgs() << "Malformed PHI in BB#" << MBB->getNumber() << ": " << *MI;
 dbgs() << "  missing input from predecessor BB#"
 << PredBB->getNumber() << '\n';
-llvm_unreachable(0);
+llvm_unreachable(nullptr);
 }
 }
 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2) {
 MachineBasicBlock *PHIBB = MI->getOperand(i+1).getMBB();
 if (CheckExtra && !Preds.count(PHIBB)) {
 dbgs() << "Warning: malformed PHI in BB#" << MBB->getNumber()
 << ": " << *MI;
 dbgs() << "  extra input from predecessor BB#"
 << PHIBB->getNumber() << '\n';
-llvm_unreachable(0);
+llvm_unreachable(nullptr);
 }
 if (PHIBB->getNumber() < 0) {
 dbgs() << "Malformed PHI in BB#" << MBB->getNumber() << ": " << *MI;
 dbgs() << "  non-existing BB#" << PHIBB->getNumber() << '\n';
-llvm_unreachable(0);
+llvm_unreachable(nullptr);
 }
 }
 ++MI;
 }
 }
 SSAUpdate.Initialize(VReg);
 // If the original definition is still around, add it as an available
 // value.
 MachineInstr *DefMI = MRI->getVRegDef(VReg);
-MachineBasicBlock *DefBB = 0;
+MachineBasicBlock *DefBB = nullptr;
 if (DefMI) {
 DefBB = DefMI->getParent();
 SSAUpdate.AddAvailableValue(DefBB, VReg);
 }
 }
 // Rewrite uses that are outside of the original def's block.
 MachineRegisterInfo::use_iterator UI = MRI->use_begin(VReg);
 while (UI != MRI->use_end()) {
-MachineOperand &UseMO = UI.getOperand();
+MachineOperand &UseMO = *UI;
-MachineInstr *UseMI = &*UI;
+MachineInstr *UseMI = UseMO.getParent();
 ++UI;
 if (UseMI->isDebugValue()) {
 // SSAUpdate can replace the use with an undef. That creates
 // a debug instruction that is a kill.
 // FIXME: Should it SSAUpdate job to delete debug instructions
 return MadeChange;
 }
 static bool isDefLiveOut(unsigned Reg, MachineBasicBlock *BB,
 const MachineRegisterInfo *MRI) {
-for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
+for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
-UE = MRI->use_end(); UI != UE; ++UI) {
+if (UseMI.isDebugValue())
-MachineInstr *UseMI = &*UI;
+continue;
-if (UseMI->isDebugValue())
+if (UseMI.getParent() != BB)
-continue;
-if (UseMI->getParent() != BB)
 return true;
 }
 return false;
 }
 // Remember which registers are used by phis in this block. This is
 // used to determine which registers are liveout while modifying the
 // block (which is why we need to copy the information).
 static void getRegsUsedByPHIs(const MachineBasicBlock &BB,
 DenseSet<unsigned> *UsedByPhi) {
-for(MachineBasicBlock::const_iterator I = BB.begin(), E = BB.end();
+for (const auto &MI : BB) {
-I != E; ++I) {
-const MachineInstr &MI = *I;
 if (!MI.isPHI())
 break;
 for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) {
 unsigned SrcReg = MI.getOperand(i).getReg();
 UsedByPhi->insert(SrcReg);
 MachineBasicBlock *PredBB = *PI;
 if (PredBB->succ_size() > 1)
 return false;
-MachineBasicBlock *PredTBB = NULL, *PredFBB = NULL;
+MachineBasicBlock *PredTBB = nullptr, *PredFBB = nullptr;
 SmallVector<MachineOperand, 4> PredCond;
 if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true))
 return false;
 if (!PredCond.empty())
 continue;
 if (bothUsedInPHI(*PredBB, Succs))
 continue;
-MachineBasicBlock *PredTBB = NULL, *PredFBB = NULL;
+MachineBasicBlock *PredTBB = nullptr, *PredFBB = nullptr;
 SmallVector<MachineOperand, 4> PredCond;
 if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true))
 continue;
 Changed = true;
 DEBUG(dbgs() << "\nTail-duplicating into PredBB: " << *PredBB
 << "From simple Succ: " << *TailBB);
 MachineBasicBlock *NewTarget = *TailBB->succ_begin();
-MachineBasicBlock *NextBB = llvm::next(MachineFunction::iterator(PredBB));
+MachineBasicBlock *NextBB = std::next(MachineFunction::iterator(PredBB));
 // Make PredFBB explicit.
 if (PredCond.empty())
 PredFBB = PredTBB;
 PredTBB = NewTarget;
 // Make the branch unconditional if possible
 if (PredTBB == PredFBB) {
 PredCond.clear();
-PredFBB = NULL;
+PredFBB = nullptr;
 }
 // Avoid adding fall through branches.
 if (PredFBB == NextBB)
-PredFBB = NULL;
+PredFBB = nullptr;
-if (PredTBB == NextBB && PredFBB == NULL)
+if (PredTBB == NextBB && PredFBB == nullptr)
-PredTBB = NULL;
+PredTBB = nullptr;
 TII->RemoveBranch(*PredBB);
 if (PredTBB)
 TII->InsertBranch(*PredBB, PredTBB, PredFBB, PredCond, DebugLoc());
+uint32_t Weight = MBPI->getEdgeWeight(PredBB, TailBB);
 PredBB->removeSuccessor(TailBB);
 unsigned NumSuccessors = PredBB->succ_size();
 assert(NumSuccessors <= 1);
 if (NumSuccessors == 0 || *PredBB->succ_begin() != NewTarget)
-PredBB->addSuccessor(NewTarget);
+PredBB->addSuccessor(NewTarget, Weight);
 TDBBs.push_back(PredBB);
 }
 return Changed;
 }
 if (RS && !TailBB->livein_empty()) {
 // Update PredBB livein.
 RS->enterBasicBlock(PredBB);
 if (!PredBB->empty())
-RS->forward(prior(PredBB->end()));
+RS->forward(std::prev(PredBB->end()));
-BitVector RegsLiveAtExit(TRI->getNumRegs());
-RS->getRegsUsed(RegsLiveAtExit, false);
 for (MachineBasicBlock::livein_iterator I = TailBB->livein_begin(),
 E = TailBB->livein_end(); I != E; ++I) {
-if (!RegsLiveAtExit[*I])
+if (!RS->isRegUsed(*I, false))
 // If a register is previously livein to the tail but it's not live
 // at the end of predecessor BB, then it should be added to its
 // livein list.
 PredBB->addLiveIn(*I);
 }
 PredBB->removeSuccessor(PredBB->succ_begin());
 assert(PredBB->succ_empty() &&
 "TailDuplicate called on block with multiple successors!");
 for (MachineBasicBlock::succ_iterator I = TailBB->succ_begin(),
 E = TailBB->succ_end(); I != E; ++I)
-PredBB->addSuccessor(*I);
+PredBB->addSuccessor(*I, MBPI->getEdgeWeight(TailBB, I));
 Changed = true;
 ++NumTailDups;
 }
 // If TailBB was duplicated into all its predecessors except for the prior
 // block, which falls through unconditionally, move the contents of this
 // block into the prior block.
-MachineBasicBlock *PrevBB = prior(MachineFunction::iterator(TailBB));
+MachineBasicBlock *PrevBB = std::prev(MachineFunction::iterator(TailBB));
-MachineBasicBlock *PriorTBB = 0, *PriorFBB = 0;
+MachineBasicBlock *PriorTBB = nullptr, *PriorFBB = nullptr;
 SmallVector<MachineOperand, 4> PriorCond;
 // This has to check PrevBB->succ_size() because EH edges are ignored by
 // AnalyzeBranch.
 if (PrevBB->succ_size() == 1 &&
 !TII->AnalyzeBranch(*PrevBB, PriorTBB, PriorFBB, PriorCond, true) &&

Mercurial > hg > CbC > CbC_llvm

comparison lib/CodeGen/TailDuplication.cpp @ 77:54457678186b LLVM3.6