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comparison lib/Target/ARM/ARMCallingConv.h @ 77:54457678186b LLVM3.6

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LLVM 3.6
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Mon, 08 Sep 2014 22:06:00 +0900
parents 95c75e76d11b
children 60c9769439b8
comparison
equal deleted inserted replaced
34:e874dbf0ad9d 77:54457678186b
10 // This file contains the custom routines for the ARM Calling Convention that 10 // This file contains the custom routines for the ARM Calling Convention that
11 // aren't done by tablegen. 11 // aren't done by tablegen.
12 // 12 //
13 //===----------------------------------------------------------------------===// 13 //===----------------------------------------------------------------------===//
14 14
15 #ifndef ARMCALLINGCONV_H 15 #ifndef LLVM_LIB_TARGET_ARM_ARMCALLINGCONV_H
16 #define ARMCALLINGCONV_H 16 #define LLVM_LIB_TARGET_ARM_ARMCALLINGCONV_H
17 17
18 #include "ARM.h" 18 #include "ARM.h"
19 #include "ARMBaseInstrInfo.h" 19 #include "ARMBaseInstrInfo.h"
20 #include "ARMSubtarget.h" 20 #include "ARMSubtarget.h"
21 #include "llvm/CodeGen/CallingConvLower.h" 21 #include "llvm/CodeGen/CallingConvLower.h"
26 26
27 // APCS f64 is in register pairs, possibly split to stack 27 // APCS f64 is in register pairs, possibly split to stack
28 static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 28 static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
29 CCValAssign::LocInfo &LocInfo, 29 CCValAssign::LocInfo &LocInfo,
30 CCState &State, bool CanFail) { 30 CCState &State, bool CanFail) {
31 static const uint16_t RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; 31 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
32 32
33 // Try to get the first register. 33 // Try to get the first register.
34 if (unsigned Reg = State.AllocateReg(RegList, 4)) 34 if (unsigned Reg = State.AllocateReg(RegList, 4))
35 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 35 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
36 else { 36 else {
69 69
70 // AAPCS f64 is in aligned register pairs 70 // AAPCS f64 is in aligned register pairs
71 static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 71 static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
72 CCValAssign::LocInfo &LocInfo, 72 CCValAssign::LocInfo &LocInfo,
73 CCState &State, bool CanFail) { 73 CCState &State, bool CanFail) {
74 static const uint16_t HiRegList[] = { ARM::R0, ARM::R2 }; 74 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
75 static const uint16_t LoRegList[] = { ARM::R1, ARM::R3 }; 75 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
76 static const uint16_t ShadowRegList[] = { ARM::R0, ARM::R1 }; 76 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 };
77 static const uint16_t GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; 77 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
78 78
79 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2); 79 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2);
80 if (Reg == 0) { 80 if (Reg == 0) {
81 81
82 // If we had R3 unallocated only, now we still must to waste it. 82 // If we had R3 unallocated only, now we still must to waste it.
121 return true; // we handled it 121 return true; // we handled it
122 } 122 }
123 123
124 static bool f64RetAssign(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 124 static bool f64RetAssign(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
125 CCValAssign::LocInfo &LocInfo, CCState &State) { 125 CCValAssign::LocInfo &LocInfo, CCState &State) {
126 static const uint16_t HiRegList[] = { ARM::R0, ARM::R2 }; 126 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
127 static const uint16_t LoRegList[] = { ARM::R1, ARM::R3 }; 127 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
128 128
129 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2); 129 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
130 if (Reg == 0) 130 if (Reg == 0)
131 return false; // we didn't handle it 131 return false; // we didn't handle it
132 132
158 CCState &State) { 158 CCState &State) {
159 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, 159 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
160 State); 160 State);
161 } 161 }
162 162
163 static const uint16_t SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
164 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
165 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
166 ARM::S12, ARM::S13, ARM::S14, ARM::S15 };
167 static const uint16_t DRegList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3,
168 ARM::D4, ARM::D5, ARM::D6, ARM::D7 };
169 static const uint16_t QRegList[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 };
170
171 // Allocate part of an AAPCS HFA or HVA. We assume that each member of the HA
172 // has InConsecutiveRegs set, and that the last member also has
173 // InConsecutiveRegsLast set. We must process all members of the HA before
174 // we can allocate it, as we need to know the total number of registers that
175 // will be needed in order to (attempt to) allocate a contiguous block.
176 static bool CC_ARM_AAPCS_Custom_HA(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
177 CCValAssign::LocInfo &LocInfo,
178 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
179 SmallVectorImpl<CCValAssign> &PendingHAMembers = State.getPendingLocs();
180
181 // AAPCS HFAs must have 1-4 elements, all of the same type
182 assert(PendingHAMembers.size() < 4);
183 if (PendingHAMembers.size() > 0)
184 assert(PendingHAMembers[0].getLocVT() == LocVT);
185
186 // Add the argument to the list to be allocated once we know the size of the
187 // HA
188 PendingHAMembers.push_back(
189 CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo));
190
191 if (ArgFlags.isInConsecutiveRegsLast()) {
192 assert(PendingHAMembers.size() > 0 && PendingHAMembers.size() <= 4 &&
193 "Homogeneous aggregates must have between 1 and 4 members");
194
195 // Try to allocate a contiguous block of registers, each of the correct
196 // size to hold one member.
197 const uint16_t *RegList;
198 unsigned NumRegs;
199 switch (LocVT.SimpleTy) {
200 case MVT::f32:
201 RegList = SRegList;
202 NumRegs = 16;
203 break;
204 case MVT::f64:
205 RegList = DRegList;
206 NumRegs = 8;
207 break;
208 case MVT::v2f64:
209 RegList = QRegList;
210 NumRegs = 4;
211 break;
212 default:
213 llvm_unreachable("Unexpected member type for HA");
214 break;
215 }
216
217 unsigned RegResult =
218 State.AllocateRegBlock(RegList, NumRegs, PendingHAMembers.size());
219
220 if (RegResult) {
221 for (SmallVectorImpl<CCValAssign>::iterator It = PendingHAMembers.begin();
222 It != PendingHAMembers.end(); ++It) {
223 It->convertToReg(RegResult);
224 State.addLoc(*It);
225 ++RegResult;
226 }
227 PendingHAMembers.clear();
228 return true;
229 }
230
231 // Register allocation failed, fall back to the stack
232
233 // Mark all VFP regs as unavailable (AAPCS rule C.2.vfp)
234 for (unsigned regNo = 0; regNo < 16; ++regNo)
235 State.AllocateReg(SRegList[regNo]);
236
237 unsigned Size = LocVT.getSizeInBits() / 8;
238 unsigned Align = std::min(Size, 8U);
239
240 for (auto It : PendingHAMembers) {
241 It.convertToMem(State.AllocateStack(Size, Align));
242 State.addLoc(It);
243 }
244
245 // All pending members have now been allocated
246 PendingHAMembers.clear();
247 }
248
249 // This will be allocated by the last member of the HA
250 return true;
251 }
252
163 } // End llvm namespace 253 } // End llvm namespace
164 254
165 #endif 255 #endif