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comparison lib/Target/MSP430/MSP430ISelDAGToDAG.cpp @ 77:54457678186b LLVM3.6

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LLVM 3.6
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Mon, 08 Sep 2014 22:06:00 +0900
parents 95c75e76d11b
children 60c9769439b8
comparison
equal deleted inserted replaced
34:e874dbf0ad9d 77:54457678186b
29 #include "llvm/Support/ErrorHandling.h" 29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/raw_ostream.h" 30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/Target/TargetLowering.h" 31 #include "llvm/Target/TargetLowering.h"
32 using namespace llvm; 32 using namespace llvm;
33 33
34 #define DEBUG_TYPE "msp430-isel"
35
34 namespace { 36 namespace {
35 struct MSP430ISelAddressMode { 37 struct MSP430ISelAddressMode {
36 enum { 38 enum {
37 RegBase, 39 RegBase,
38 FrameIndexBase 40 FrameIndexBase
50 const char *ES; 52 const char *ES;
51 int JT; 53 int JT;
52 unsigned Align; // CP alignment. 54 unsigned Align; // CP alignment.
53 55
54 MSP430ISelAddressMode() 56 MSP430ISelAddressMode()
55 : BaseType(RegBase), Disp(0), GV(0), CP(0), BlockAddr(0), 57 : BaseType(RegBase), Disp(0), GV(nullptr), CP(nullptr),
56 ES(0), JT(-1), Align(0) { 58 BlockAddr(nullptr), ES(nullptr), JT(-1), Align(0) {
57 } 59 }
58 60
59 bool hasSymbolicDisplacement() const { 61 bool hasSymbolicDisplacement() const {
60 return GV != 0 || CP != 0 || ES != 0 || JT != -1; 62 return GV != nullptr || CP != nullptr || ES != nullptr || JT != -1;
61 } 63 }
62 64
63 void dump() { 65 void dump() {
64 errs() << "MSP430ISelAddressMode " << this << '\n'; 66 errs() << "MSP430ISelAddressMode " << this << '\n';
65 if (BaseType == RegBase && Base.Reg.getNode() != 0) { 67 if (BaseType == RegBase && Base.Reg.getNode() != nullptr) {
66 errs() << "Base.Reg "; 68 errs() << "Base.Reg ";
67 Base.Reg.getNode()->dump(); 69 Base.Reg.getNode()->dump();
68 } else if (BaseType == FrameIndexBase) { 70 } else if (BaseType == FrameIndexBase) {
69 errs() << " Base.FrameIndex " << Base.FrameIndex << '\n'; 71 errs() << " Base.FrameIndex " << Base.FrameIndex << '\n';
70 } 72 }
93 const MSP430TargetLowering &Lowering; 95 const MSP430TargetLowering &Lowering;
94 const MSP430Subtarget &Subtarget; 96 const MSP430Subtarget &Subtarget;
95 97
96 public: 98 public:
97 MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel) 99 MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel)
98 : SelectionDAGISel(TM, OptLevel), 100 : SelectionDAGISel(TM, OptLevel),
99 Lowering(*TM.getTargetLowering()), 101 Lowering(*TM.getSubtargetImpl()->getTargetLowering()),
100 Subtarget(*TM.getSubtargetImpl()) { } 102 Subtarget(*TM.getSubtargetImpl()) {}
101 103
102 virtual const char *getPassName() const { 104 const char *getPassName() const override {
103 return "MSP430 DAG->DAG Pattern Instruction Selection"; 105 return "MSP430 DAG->DAG Pattern Instruction Selection";
104 } 106 }
105 107
106 bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM); 108 bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
107 bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM); 109 bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
108 bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM); 110 bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
109 111
110 virtual bool 112 bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
111 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, 113 std::vector<SDValue> &OutOps) override;
112 std::vector<SDValue> &OutOps);
113 114
114 // Include the pieces autogenerated from the target description. 115 // Include the pieces autogenerated from the target description.
115 #include "MSP430GenDAGISel.inc" 116 #include "MSP430GenDAGISel.inc"
116 117
117 private: 118 private:
118 SDNode *Select(SDNode *N); 119 SDNode *Select(SDNode *N) override;
119 SDNode *SelectIndexedLoad(SDNode *Op); 120 SDNode *SelectIndexedLoad(SDNode *Op);
120 SDNode *SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2, 121 SDNode *SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
121 unsigned Opc8, unsigned Opc16); 122 unsigned Opc8, unsigned Opc16);
122 123
123 bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp); 124 bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp);
197 return false; 198 return false;
198 break; 199 break;
199 200
200 case ISD::FrameIndex: 201 case ISD::FrameIndex:
201 if (AM.BaseType == MSP430ISelAddressMode::RegBase 202 if (AM.BaseType == MSP430ISelAddressMode::RegBase
202 && AM.Base.Reg.getNode() == 0) { 203 && AM.Base.Reg.getNode() == nullptr) {
203 AM.BaseType = MSP430ISelAddressMode::FrameIndexBase; 204 AM.BaseType = MSP430ISelAddressMode::FrameIndexBase;
204 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex(); 205 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
205 return false; 206 return false;
206 } 207 }
207 break; 208 break;
226 MSP430ISelAddressMode Backup = AM; 227 MSP430ISelAddressMode Backup = AM;
227 uint64_t Offset = CN->getSExtValue(); 228 uint64_t Offset = CN->getSExtValue();
228 // Start with the LHS as an addr mode. 229 // Start with the LHS as an addr mode.
229 if (!MatchAddress(N.getOperand(0), AM) && 230 if (!MatchAddress(N.getOperand(0), AM) &&
230 // Address could not have picked a GV address for the displacement. 231 // Address could not have picked a GV address for the displacement.
231 AM.GV == NULL && 232 AM.GV == nullptr &&
232 // Check to see if the LHS & C is zero. 233 // Check to see if the LHS & C is zero.
233 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) { 234 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
234 AM.Disp += Offset; 235 AM.Disp += Offset;
235 return false; 236 return false;
236 } 237 }
328 } 329 }
329 330
330 SDNode *MSP430DAGToDAGISel::SelectIndexedLoad(SDNode *N) { 331 SDNode *MSP430DAGToDAGISel::SelectIndexedLoad(SDNode *N) {
331 LoadSDNode *LD = cast<LoadSDNode>(N); 332 LoadSDNode *LD = cast<LoadSDNode>(N);
332 if (!isValidIndexedLoad(LD)) 333 if (!isValidIndexedLoad(LD))
333 return NULL; 334 return nullptr;
334 335
335 MVT VT = LD->getMemoryVT().getSimpleVT(); 336 MVT VT = LD->getMemoryVT().getSimpleVT();
336 337
337 unsigned Opcode = 0; 338 unsigned Opcode = 0;
338 switch (VT.SimpleTy) { 339 switch (VT.SimpleTy) {
341 break; 342 break;
342 case MVT::i16: 343 case MVT::i16:
343 Opcode = MSP430::MOV16rm_POST; 344 Opcode = MSP430::MOV16rm_POST;
344 break; 345 break;
345 default: 346 default:
346 return NULL; 347 return nullptr;
347 } 348 }
348 349
349 return CurDAG->getMachineNode(Opcode, SDLoc(N), 350 return CurDAG->getMachineNode(Opcode, SDLoc(N),
350 VT, MVT::i16, MVT::Other, 351 VT, MVT::i16, MVT::Other,
351 LD->getBasePtr(), LD->getChain()); 352 LD->getBasePtr(), LD->getChain());
357 if (N1.getOpcode() == ISD::LOAD && 358 if (N1.getOpcode() == ISD::LOAD &&
358 N1.hasOneUse() && 359 N1.hasOneUse() &&
359 IsLegalToFold(N1, Op, Op, OptLevel)) { 360 IsLegalToFold(N1, Op, Op, OptLevel)) {
360 LoadSDNode *LD = cast<LoadSDNode>(N1); 361 LoadSDNode *LD = cast<LoadSDNode>(N1);
361 if (!isValidIndexedLoad(LD)) 362 if (!isValidIndexedLoad(LD))
362 return NULL; 363 return nullptr;
363 364
364 MVT VT = LD->getMemoryVT().getSimpleVT(); 365 MVT VT = LD->getMemoryVT().getSimpleVT();
365 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8); 366 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8);
366 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1); 367 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
367 MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand(); 368 MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
368 SDValue Ops0[] = { N2, LD->getBasePtr(), LD->getChain() }; 369 SDValue Ops0[] = { N2, LD->getBasePtr(), LD->getChain() };
369 SDNode *ResNode = 370 SDNode *ResNode =
370 CurDAG->SelectNodeTo(Op, Opc, 371 CurDAG->SelectNodeTo(Op, Opc, VT, MVT::i16, MVT::Other, Ops0);
371 VT, MVT::i16, MVT::Other,
372 Ops0, 3);
373 cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1); 372 cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
374 // Transfer chain. 373 // Transfer chain.
375 ReplaceUses(SDValue(N1.getNode(), 2), SDValue(ResNode, 2)); 374 ReplaceUses(SDValue(N1.getNode(), 2), SDValue(ResNode, 2));
376 // Transfer writeback. 375 // Transfer writeback.
377 ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1)); 376 ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
378 return ResNode; 377 return ResNode;
379 } 378 }
380 379
381 return NULL; 380 return nullptr;
382 } 381 }
383 382
384 383
385 SDNode *MSP430DAGToDAGISel::Select(SDNode *Node) { 384 SDNode *MSP430DAGToDAGISel::Select(SDNode *Node) {
386 SDLoc dl(Node); 385 SDLoc dl(Node);
394 if (Node->isMachineOpcode()) { 393 if (Node->isMachineOpcode()) {
395 DEBUG(errs() << "== "; 394 DEBUG(errs() << "== ";
396 Node->dump(CurDAG); 395 Node->dump(CurDAG);
397 errs() << "\n"); 396 errs() << "\n");
398 Node->setNodeId(-1); 397 Node->setNodeId(-1);
399 return NULL; 398 return nullptr;
400 } 399 }
401 400
402 // Few custom selection stuff. 401 // Few custom selection stuff.
403 switch (Node->getOpcode()) { 402 switch (Node->getOpcode()) {
404 default: break; 403 default: break;
482 481
483 // Select the default instruction 482 // Select the default instruction
484 SDNode *ResNode = SelectCode(Node); 483 SDNode *ResNode = SelectCode(Node);
485 484
486 DEBUG(errs() << "=> "); 485 DEBUG(errs() << "=> ");
487 if (ResNode == NULL || ResNode == Node) 486 if (ResNode == nullptr || ResNode == Node)
488 DEBUG(Node->dump(CurDAG)); 487 DEBUG(Node->dump(CurDAG));
489 else 488 else
490 DEBUG(ResNode->dump(CurDAG)); 489 DEBUG(ResNode->dump(CurDAG));
491 DEBUG(errs() << "\n"); 490 DEBUG(errs() << "\n");
492 491