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comparison lib/Target/MSP430/MSP430InstrInfo.h @ 77:54457678186b LLVM3.6

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LLVM 3.6
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Mon, 08 Sep 2014 22:06:00 +0900
parents 95c75e76d11b
children afa8332a0e37
comparison
equal deleted inserted replaced
34:e874dbf0ad9d 77:54457678186b
9 // 9 //
10 // This file contains the MSP430 implementation of the TargetInstrInfo class. 10 // This file contains the MSP430 implementation of the TargetInstrInfo class.
11 // 11 //
12 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===//
13 13
14 #ifndef LLVM_TARGET_MSP430INSTRINFO_H 14 #ifndef LLVM_LIB_TARGET_MSP430_MSP430INSTRINFO_H
15 #define LLVM_TARGET_MSP430INSTRINFO_H 15 #define LLVM_LIB_TARGET_MSP430_MSP430INSTRINFO_H
16 16
17 #include "MSP430RegisterInfo.h" 17 #include "MSP430RegisterInfo.h"
18 #include "llvm/Target/TargetInstrInfo.h" 18 #include "llvm/Target/TargetInstrInfo.h"
19 19
20 #define GET_INSTRINFO_HEADER 20 #define GET_INSTRINFO_HEADER
21 #include "MSP430GenInstrInfo.inc" 21 #include "MSP430GenInstrInfo.inc"
22 22
23 namespace llvm { 23 namespace llvm {
24 24
25 class MSP430TargetMachine; 25 class MSP430Subtarget;
26 26
27 /// MSP430II - This namespace holds all of the target specific flags that 27 /// MSP430II - This namespace holds all of the target specific flags that
28 /// instruction info tracks. 28 /// instruction info tracks.
29 /// 29 ///
30 namespace MSP430II { 30 namespace MSP430II {
42 42
43 class MSP430InstrInfo : public MSP430GenInstrInfo { 43 class MSP430InstrInfo : public MSP430GenInstrInfo {
44 const MSP430RegisterInfo RI; 44 const MSP430RegisterInfo RI;
45 virtual void anchor(); 45 virtual void anchor();
46 public: 46 public:
47 explicit MSP430InstrInfo(MSP430TargetMachine &TM); 47 explicit MSP430InstrInfo(MSP430Subtarget &STI);
48 48
49 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 49 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
50 /// such, whenever a client has an instance of instruction info, it should 50 /// such, whenever a client has an instance of instruction info, it should
51 /// always be able to get register info as well (through this method). 51 /// always be able to get register info as well (through this method).
52 /// 52 ///
53 virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } 53 const TargetRegisterInfo &getRegisterInfo() const { return RI; }
54 54
55 void copyPhysReg(MachineBasicBlock &MBB, 55 void copyPhysReg(MachineBasicBlock &MBB,
56 MachineBasicBlock::iterator I, DebugLoc DL, 56 MachineBasicBlock::iterator I, DebugLoc DL,
57 unsigned DestReg, unsigned SrcReg, 57 unsigned DestReg, unsigned SrcReg,
58 bool KillSrc) const; 58 bool KillSrc) const override;
59 59
60 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 60 void storeRegToStackSlot(MachineBasicBlock &MBB,
61 MachineBasicBlock::iterator MI, 61 MachineBasicBlock::iterator MI,
62 unsigned SrcReg, bool isKill, 62 unsigned SrcReg, bool isKill,
63 int FrameIndex, 63 int FrameIndex,
64 const TargetRegisterClass *RC, 64 const TargetRegisterClass *RC,
65 const TargetRegisterInfo *TRI) const; 65 const TargetRegisterInfo *TRI) const override;
66 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 66 void loadRegFromStackSlot(MachineBasicBlock &MBB,
67 MachineBasicBlock::iterator MI, 67 MachineBasicBlock::iterator MI,
68 unsigned DestReg, int FrameIdx, 68 unsigned DestReg, int FrameIdx,
69 const TargetRegisterClass *RC, 69 const TargetRegisterClass *RC,
70 const TargetRegisterInfo *TRI) const; 70 const TargetRegisterInfo *TRI) const override;
71 71
72 unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 72 unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
73 73
74 // Branch folding goodness 74 // Branch folding goodness
75 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 75 bool
76 bool isUnpredicatedTerminator(const MachineInstr *MI) const; 76 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
77 bool isUnpredicatedTerminator(const MachineInstr *MI) const override;
77 bool AnalyzeBranch(MachineBasicBlock &MBB, 78 bool AnalyzeBranch(MachineBasicBlock &MBB,
78 MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, 79 MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
79 SmallVectorImpl<MachineOperand> &Cond, 80 SmallVectorImpl<MachineOperand> &Cond,
80 bool AllowModify) const; 81 bool AllowModify) const override;
81 82
82 unsigned RemoveBranch(MachineBasicBlock &MBB) const; 83 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
83 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 84 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
84 MachineBasicBlock *FBB, 85 MachineBasicBlock *FBB,
85 const SmallVectorImpl<MachineOperand> &Cond, 86 const SmallVectorImpl<MachineOperand> &Cond,
86 DebugLoc DL) const; 87 DebugLoc DL) const override;
87 88
88 }; 89 };
89 90
90 } 91 }
91 92