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comparison lib/Target/Mips/Mips16ISelDAGToDAG.cpp @ 77:54457678186b LLVM3.6

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LLVM 3.6
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Mon, 08 Sep 2014 22:06:00 +0900
parents 95c75e76d11b
children 60c9769439b8
comparison
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34:e874dbf0ad9d 77:54457678186b
9 // 9 //
10 // Subclass of MipsDAGToDAGISel specialized for mips16. 10 // Subclass of MipsDAGToDAGISel specialized for mips16.
11 // 11 //
12 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===//
13 13
14 #define DEBUG_TYPE "mips-isel"
15 #include "Mips16ISelDAGToDAG.h" 14 #include "Mips16ISelDAGToDAG.h"
15 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "Mips.h" 16 #include "Mips.h"
17 #include "MCTargetDesc/MipsBaseInfo.h"
18 #include "MipsAnalyzeImmediate.h" 17 #include "MipsAnalyzeImmediate.h"
19 #include "MipsMachineFunction.h" 18 #include "MipsMachineFunction.h"
20 #include "MipsRegisterInfo.h" 19 #include "MipsRegisterInfo.h"
21 #include "llvm/CodeGen/MachineConstantPool.h" 20 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h" 24 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGNodes.h" 25 #include "llvm/CodeGen/SelectionDAGNodes.h"
26 #include "llvm/IR/CFG.h"
27 #include "llvm/IR/GlobalValue.h" 27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Instructions.h" 28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h" 29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h" 30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/CFG.h"
32 #include "llvm/Support/Debug.h" 31 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h" 32 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h" 33 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetMachine.h" 34 #include "llvm/Target/TargetMachine.h"
36 using namespace llvm; 35 using namespace llvm;
37 36
37 #define DEBUG_TYPE "mips-isel"
38
38 bool Mips16DAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { 39 bool Mips16DAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
39 if (!Subtarget.inMips16Mode()) 40 Subtarget = &TM.getSubtarget<MipsSubtarget>();
41 if (!Subtarget->inMips16Mode())
40 return false; 42 return false;
41 return MipsDAGToDAGISel::runOnMachineFunction(MF); 43 return MipsDAGToDAGISel::runOnMachineFunction(MF);
42 } 44 }
43 /// Select multiply instructions. 45 /// Select multiply instructions.
44 std::pair<SDNode*, SDNode*> 46 std::pair<SDNode*, SDNode*>
45 Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, SDLoc DL, EVT Ty, 47 Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, SDLoc DL, EVT Ty,
46 bool HasLo, bool HasHi) { 48 bool HasLo, bool HasHi) {
47 SDNode *Lo = 0, *Hi = 0; 49 SDNode *Lo = nullptr, *Hi = nullptr;
48 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0), 50 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
49 N->getOperand(1)); 51 N->getOperand(1));
50 SDValue InFlag = SDValue(Mul, 0); 52 SDValue InFlag = SDValue(Mul, 0);
51 53
52 if (HasLo) { 54 if (HasLo) {
68 return; 70 return;
69 71
70 MachineBasicBlock &MBB = MF.front(); 72 MachineBasicBlock &MBB = MF.front();
71 MachineBasicBlock::iterator I = MBB.begin(); 73 MachineBasicBlock::iterator I = MBB.begin();
72 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 74 MachineRegisterInfo &RegInfo = MF.getRegInfo();
73 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 75 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
74 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); 76 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
75 unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(); 77 unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();
76 const TargetRegisterClass *RC = 78 const TargetRegisterClass *RC =
77 (const TargetRegisterClass*)&Mips::CPU16RegsRegClass; 79 (const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
78 80
99 if (!MipsFI->mips16SPAliasRegSet()) 101 if (!MipsFI->mips16SPAliasRegSet())
100 return; 102 return;
101 103
102 MachineBasicBlock &MBB = MF.front(); 104 MachineBasicBlock &MBB = MF.front();
103 MachineBasicBlock::iterator I = MBB.begin(); 105 MachineBasicBlock::iterator I = MBB.begin();
104 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 106 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
105 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); 107 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
106 unsigned Mips16SPAliasReg = MipsFI->getMips16SPAliasReg(); 108 unsigned Mips16SPAliasReg = MipsFI->getMips16SPAliasReg();
107 109
108 BuildMI(MBB, I, DL, TII.get(Mips::MoveR3216), Mips16SPAliasReg) 110 BuildMI(MBB, I, DL, TII.get(Mips::MoveR3216), Mips16SPAliasReg)
109 .addReg(Mips::SP); 111 .addReg(Mips::SP);
131 case ISD::LOAD: { 133 case ISD::LOAD: {
132 LoadSDNode *SD = dyn_cast<LoadSDNode>(Parent); 134 LoadSDNode *SD = dyn_cast<LoadSDNode>(Parent);
133 switch (SD->getMemoryVT().getSizeInBits()) { 135 switch (SD->getMemoryVT().getSizeInBits()) {
134 case 8: 136 case 8:
135 case 16: 137 case 16:
136 AliasReg = TM.getFrameLowering()->hasFP(*MF)? 138 AliasReg = TM.getSubtargetImpl()->getFrameLowering()->hasFP(*MF)
137 AliasFPReg: getMips16SPAliasReg(); 139 ? AliasFPReg
140 : getMips16SPAliasReg();
138 return; 141 return;
139 } 142 }
140 break; 143 break;
141 } 144 }
142 case ISD::STORE: { 145 case ISD::STORE: {
143 StoreSDNode *SD = dyn_cast<StoreSDNode>(Parent); 146 StoreSDNode *SD = dyn_cast<StoreSDNode>(Parent);
144 switch (SD->getMemoryVT().getSizeInBits()) { 147 switch (SD->getMemoryVT().getSizeInBits()) {
145 case 8: 148 case 8:
146 case 16: 149 case 16:
147 AliasReg = TM.getFrameLowering()->hasFP(*MF)? 150 AliasReg = TM.getSubtargetImpl()->getFrameLowering()->hasFP(*MF)
148 AliasFPReg: getMips16SPAliasReg(); 151 ? AliasFPReg
152 : getMips16SPAliasReg();
149 return; 153 return;
150 } 154 }
151 break; 155 break;
152 } 156 }
153 } 157 }
222 } 226 }
223 227
224 // If an indexed floating point load/store can be emitted, return false. 228 // If an indexed floating point load/store can be emitted, return false.
225 const LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(Parent); 229 const LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(Parent);
226 230
227 if (LS && 231 if (LS) {
228 (LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) && 232 if (LS->getMemoryVT() == MVT::f32 && Subtarget->hasMips4_32r2())
229 Subtarget.hasFPIdx()) 233 return false;
230 return false; 234 if (LS->getMemoryVT() == MVT::f64 && Subtarget->hasMips4_32r2())
235 return false;
236 }
231 } 237 }
232 Base = Addr; 238 Base = Addr;
233 Offset = CurDAG->getTargetConstant(0, ValTy); 239 Offset = CurDAG->getTargetConstant(0, ValTy);
234 return true; 240 return true;
235 } 241 }
295 ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0)); 301 ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
296 302
297 if (!SDValue(Node, 1).use_empty()) 303 if (!SDValue(Node, 1).use_empty())
298 ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0)); 304 ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
299 305
300 return std::make_pair(true, (SDNode*)NULL); 306 return std::make_pair(true, nullptr);
301 } 307 }
302 308
303 case ISD::MULHS: 309 case ISD::MULHS:
304 case ISD::MULHU: { 310 case ISD::MULHU: {
305 MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16); 311 MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16);
306 SDNode *Result = selectMULT(Node, MultOpc, DL, NodeTy, false, true).second; 312 SDNode *Result = selectMULT(Node, MultOpc, DL, NodeTy, false, true).second;
307 return std::make_pair(true, Result); 313 return std::make_pair(true, Result);
308 } 314 }
309 } 315 }
310 316
311 return std::make_pair(false, (SDNode*)NULL); 317 return std::make_pair(false, nullptr);
312 } 318 }
313 319
314 FunctionPass *llvm::createMips16ISelDag(MipsTargetMachine &TM) { 320 FunctionPass *llvm::createMips16ISelDag(MipsTargetMachine &TM) {
315 return new Mips16DAGToDAGISel(TM); 321 return new Mips16DAGToDAGISel(TM);
316 } 322 }