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comparison lib/Target/Mips/MipsCallingConv.td @ 77:54457678186b LLVM3.6

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LLVM 3.6
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Mon, 08 Sep 2014 22:06:00 +0900
parents 95c75e76d11b
children 60c9769439b8
comparison
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34:e874dbf0ad9d 77:54457678186b
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // This describes the calling conventions for Mips architecture. 9 // This describes the calling conventions for Mips architecture.
10 //===----------------------------------------------------------------------===// 10 //===----------------------------------------------------------------------===//
11 11
12 /// CCIfSubtarget - Match if the current subtarget has a feature F. 12 /// CCIfSubtarget - Match if the current subtarget has a feature F.
13 class CCIfSubtarget<string F, CCAction A>: 13 class CCIfSubtarget<string F, CCAction A>
14 CCIf<!strconcat("State.getTarget().getSubtarget<MipsSubtarget>().", F), A>; 14 : CCIf<!strconcat("static_cast<const MipsSubtarget&>"
15 "(State.getMachineFunction().getSubtarget()).",
16 F),
17 A>;
15 18
16 //===----------------------------------------------------------------------===// 19 //===----------------------------------------------------------------------===//
17 // Mips O32 Calling Convention 20 // Mips O32 Calling Convention
18 //===----------------------------------------------------------------------===// 21 //===----------------------------------------------------------------------===//
19 22
24 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>, 27 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>,
25 28
26 // f32 are returned in registers F0, F2 29 // f32 are returned in registers F0, F2
27 CCIfType<[f32], CCAssignToReg<[F0, F2]>>, 30 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
28 31
29 // f64 arguments are returned in D0_64 and D1_64 in FP64bit mode or 32 // f64 arguments are returned in D0_64 and D2_64 in FP64bit mode or
30 // in D0 and D1 in FP32bit mode. 33 // in D0 and D1 in FP32bit mode.
31 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D1_64]>>>, 34 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D2_64]>>>,
32 CCIfType<[f64], CCIfSubtarget<"isNotFP64bit()", CCAssignToReg<[D0, D1]>>> 35 CCIfType<[f64], CCIfSubtarget<"isNotFP64bit()", CCAssignToReg<[D0, D1]>>>
33 ]>; 36 ]>;
34 37
35 //===----------------------------------------------------------------------===// 38 //===----------------------------------------------------------------------===//
36 // Mips N32/64 Calling Convention 39 // Mips N32/64 Calling Convention
152 def CC_MipsO32_FastCC : CallingConv<[ 155 def CC_MipsO32_FastCC : CallingConv<[
153 // f64 arguments are passed in double-precision floating pointer registers. 156 // f64 arguments are passed in double-precision floating pointer registers.
154 CCIfType<[f64], CCIfSubtarget<"isNotFP64bit()", 157 CCIfType<[f64], CCIfSubtarget<"isNotFP64bit()",
155 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7, 158 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7,
156 D8, D9]>>>, 159 D8, D9]>>>,
157 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", 160 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"useOddSPReg()",
158 CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, 161 CCAssignToReg<[D0_64, D1_64, D2_64, D3_64,
159 D4_64, D5_64, D6_64, D7_64, 162 D4_64, D5_64, D6_64, D7_64,
160 D8_64, D9_64, D10_64, D11_64, 163 D8_64, D9_64, D10_64, D11_64,
161 D12_64, D13_64, D14_64, D15_64, 164 D12_64, D13_64, D14_64, D15_64,
162 D16_64, D17_64, D18_64, 165 D16_64, D17_64, D18_64,
163 D19_64]>>>, 166 D19_64]>>>>,
167 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"noOddSPReg()",
168 CCAssignToReg<[D0_64, D2_64, D4_64, D6_64,
169 D8_64, D10_64, D12_64, D14_64,
170 D16_64, D18_64]>>>>,
164 171
165 // Stack parameter slots for f64 are 64-bit doublewords and 8-byte aligned. 172 // Stack parameter slots for f64 are 64-bit doublewords and 8-byte aligned.
166 CCIfType<[f64], CCAssignToStack<8, 8>> 173 CCIfType<[f64], CCAssignToStack<8, 8>>
167 ]>; 174 ]>;
168 175
190 // Promote i8/i16 arguments to i32. 197 // Promote i8/i16 arguments to i32.
191 CCIfType<[i8, i16], CCPromoteToType<i32>>, 198 CCIfType<[i8, i16], CCPromoteToType<i32>>,
192 199
193 // Integer arguments are passed in integer registers. All scratch registers, 200 // Integer arguments are passed in integer registers. All scratch registers,
194 // except for AT, V0 and T9, are available to be used as argument registers. 201 // except for AT, V0 and T9, are available to be used as argument registers.
195 CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, 202 CCIfType<[i32], CCIfSubtarget<"isNotTargetNaCl()",
196 T7, T8, V1]>>, 203 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, V1]>>>,
204
205 // In NaCl, T6, T7 and T8 are reserved and not available as argument
206 // registers for fastcc. T6 contains the mask for sandboxing control flow
207 // (indirect jumps and calls). T7 contains the mask for sandboxing memory
208 // accesses (loads and stores). T8 contains the thread pointer.
209 CCIfType<[i32], CCIfSubtarget<"isTargetNaCl()",
210 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, V1]>>>,
197 211
198 // f32 arguments are passed in single-precision floating pointer registers. 212 // f32 arguments are passed in single-precision floating pointer registers.
199 CCIfType<[f32], CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, 213 CCIfType<[f32], CCIfSubtarget<"useOddSPReg()",
200 F11, F12, F13, F14, F15, F16, F17, F18, F19]>>, 214 CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13,
215 F14, F15, F16, F17, F18, F19]>>>,
216
217 // Don't use odd numbered single-precision registers for -mno-odd-spreg.
218 CCIfType<[f32], CCIfSubtarget<"noOddSPReg()",
219 CCAssignToReg<[F0, F2, F4, F6, F8, F10, F12, F14, F16, F18]>>>,
201 220
202 // Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned. 221 // Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned.
203 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 222 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
204 223
205 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>>, 224 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>>,
230 //===----------------------------------------------------------------------===// 249 //===----------------------------------------------------------------------===//
231 250
232 def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP, 251 def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP,
233 (sequence "S%u", 7, 0))>; 252 (sequence "S%u", 7, 0))>;
234 253
254 def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
255 (sequence "S%u", 7, 0))> {
256 let OtherPreserved = (add (decimate (sequence "F%u", 30, 20), 2));
257 }
258
235 def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP, 259 def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
236 (sequence "S%u", 7, 0))>; 260 (sequence "S%u", 7, 0))>;
237 261
238 def CSR_O32_FP64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 20), RA, FP, 262 def CSR_O32_FP64 :
239 (sequence "S%u", 7, 0))>; 263 CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), RA, FP,
240 264 (sequence "S%u", 7, 0))>;
241 def CSR_N32 : CalleeSavedRegs<(add D31_64, D29_64, D27_64, D25_64, D24_64, 265
242 D23_64, D22_64, D21_64, RA_64, FP_64, GP_64, 266 def CSR_N32 : CalleeSavedRegs<(add D20_64, D22_64, D24_64, D26_64, D28_64,
267 D30_64, RA_64, FP_64, GP_64,
243 (sequence "S%u_64", 7, 0))>; 268 (sequence "S%u_64", 7, 0))>;
244 269
245 def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64, 270 def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64,
246 GP_64, (sequence "S%u_64", 7, 0))>; 271 GP_64, (sequence "S%u_64", 7, 0))>;
247 272
248 def CSR_Mips16RetHelper : 273 def CSR_Mips16RetHelper :
249 CalleeSavedRegs<(add V0, V1, (sequence "A%u", 3, 0), S0, S1)>; 274 CalleeSavedRegs<(add V0, V1, FP,
275 (sequence "A%u", 3, 0), (sequence "S%u", 7, 0),
276 (sequence "D%u", 15, 10))>;