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comparison lib/Target/Mips/MipsISelLowering.h @ 77:54457678186b LLVM3.6

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LLVM 3.6
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Mon, 08 Sep 2014 22:06:00 +0900
parents 95c75e76d11b
children 60c9769439b8
comparison
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34:e874dbf0ad9d 77:54457678186b
10 // This file defines the interfaces that Mips uses to lower LLVM code into a 10 // This file defines the interfaces that Mips uses to lower LLVM code into a
11 // selection DAG. 11 // selection DAG.
12 // 12 //
13 //===----------------------------------------------------------------------===// 13 //===----------------------------------------------------------------------===//
14 14
15 #ifndef MipsISELLOWERING_H 15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16 #define MipsISELLOWERING_H 16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
17 17
18 #include "MCTargetDesc/MipsBaseInfo.h"
18 #include "Mips.h" 19 #include "Mips.h"
19 #include "MipsSubtarget.h"
20 #include "MCTargetDesc/MipsBaseInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h" 20 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/SelectionDAG.h" 21 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/IR/Function.h" 22 #include "llvm/IR/Function.h"
24 #include "llvm/Target/TargetLowering.h" 23 #include "llvm/Target/TargetLowering.h"
25 #include <deque> 24 #include <deque>
182 ILVL, // Interleave left elements 181 ILVL, // Interleave left elements
183 ILVR, // Interleave right elements 182 ILVR, // Interleave right elements
184 PCKEV, // Pack even elements 183 PCKEV, // Pack even elements
185 PCKOD, // Pack odd elements 184 PCKOD, // Pack odd elements
186 185
186 // Vector Lane Copy
187 INSVE, // Copy element from one vector to another
188
187 // Combined (XOR (OR $a, $b), -1) 189 // Combined (XOR (OR $a, $b), -1)
188 VNOR, 190 VNOR,
189 191
190 // Extended vector element extraction 192 // Extended vector element extraction
191 VEXTRACT_SEXT_ELT, 193 VEXTRACT_SEXT_ELT,
205 207
206 //===--------------------------------------------------------------------===// 208 //===--------------------------------------------------------------------===//
207 // TargetLowering Implementation 209 // TargetLowering Implementation
208 //===--------------------------------------------------------------------===// 210 //===--------------------------------------------------------------------===//
209 class MipsFunctionInfo; 211 class MipsFunctionInfo;
212 class MipsSubtarget;
210 213
211 class MipsTargetLowering : public TargetLowering { 214 class MipsTargetLowering : public TargetLowering {
215 bool isMicroMips;
212 public: 216 public:
213 explicit MipsTargetLowering(MipsTargetMachine &TM); 217 explicit MipsTargetLowering(MipsTargetMachine &TM,
214 218 const MipsSubtarget &STI);
215 static const MipsTargetLowering *create(MipsTargetMachine &TM); 219
216 220 static const MipsTargetLowering *create(MipsTargetMachine &TM,
217 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; } 221 const MipsSubtarget &STI);
218 222
219 virtual void LowerOperationWrapper(SDNode *N, 223 /// createFastISel - This method returns a target specific FastISel object,
220 SmallVectorImpl<SDValue> &Results, 224 /// or null if the target does not support "fast" ISel.
221 SelectionDAG &DAG) const; 225 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
226 const TargetLibraryInfo *libInfo) const override;
227
228 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
229
230 void LowerOperationWrapper(SDNode *N,
231 SmallVectorImpl<SDValue> &Results,
232 SelectionDAG &DAG) const override;
222 233
223 /// LowerOperation - Provide custom lowering hooks for some operations. 234 /// LowerOperation - Provide custom lowering hooks for some operations.
224 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 235 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
225 236
226 /// ReplaceNodeResults - Replace the results of node with an illegal result 237 /// ReplaceNodeResults - Replace the results of node with an illegal result
227 /// type with new values built out of custom code. 238 /// type with new values built out of custom code.
228 /// 239 ///
229 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 240 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
230 SelectionDAG &DAG) const; 241 SelectionDAG &DAG) const override;
231 242
232 /// getTargetNodeName - This method returns the name of a target specific 243 /// getTargetNodeName - This method returns the name of a target specific
233 // DAG node. 244 // DAG node.
234 virtual const char *getTargetNodeName(unsigned Opcode) const; 245 const char *getTargetNodeName(unsigned Opcode) const override;
235 246
236 /// getSetCCResultType - get the ISD::SETCC result ValueType 247 /// getSetCCResultType - get the ISD::SETCC result ValueType
237 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const; 248 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
238 249
239 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 250 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
240 251
241 virtual MachineBasicBlock * 252 MachineBasicBlock *
242 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; 253 EmitInstrWithCustomInserter(MachineInstr *MI,
254 MachineBasicBlock *MBB) const override;
243 255
244 struct LTStr { 256 struct LTStr {
245 bool operator()(const char *S1, const char *S2) const { 257 bool operator()(const char *S1, const char *S2) const {
246 return strcmp(S1, S2) < 0; 258 return strcmp(S1, S2) < 0;
247 } 259 }
252 264
253 // This method creates the following nodes, which are necessary for 265 // This method creates the following nodes, which are necessary for
254 // computing a local symbol's address: 266 // computing a local symbol's address:
255 // 267 //
256 // (add (load (wrapper $gp, %got(sym)), %lo(sym)) 268 // (add (load (wrapper $gp, %got(sym)), %lo(sym))
257 template<class NodeTy> 269 template <class NodeTy>
258 SDValue getAddrLocal(NodeTy *N, EVT Ty, SelectionDAG &DAG, 270 SDValue getAddrLocal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
259 bool HasMips64) const { 271 bool IsN32OrN64) const {
260 SDLoc DL(N); 272 SDLoc DL(N);
261 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 273 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
262 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), 274 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
263 getTargetNode(N, Ty, DAG, GOTFlag)); 275 getTargetNode(N, Ty, DAG, GOTFlag));
264 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT, 276 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
265 MachinePointerInfo::getGOT(), false, false, 277 MachinePointerInfo::getGOT(), false, false,
266 false, 0); 278 false, 0);
267 unsigned LoFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 279 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
268 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, 280 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
269 getTargetNode(N, Ty, DAG, LoFlag)); 281 getTargetNode(N, Ty, DAG, LoFlag));
270 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo); 282 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
271 } 283 }
272 284
376 /// reservedArgArea - The size of the area the caller reserves for 388 /// reservedArgArea - The size of the area the caller reserves for
377 /// register arguments. This is 16-byte if ABI is O32. 389 /// register arguments. This is 16-byte if ABI is O32.
378 unsigned reservedArgArea() const; 390 unsigned reservedArgArea() const;
379 391
380 /// Return pointer to array of integer argument registers. 392 /// Return pointer to array of integer argument registers.
381 const uint16_t *intArgRegs() const; 393 const MCPhysReg *intArgRegs() const;
382 394
383 typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator; 395 typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator;
384 byval_iterator byval_begin() const { return ByValArgs.begin(); } 396 byval_iterator byval_begin() const { return ByValArgs.begin(); }
385 byval_iterator byval_end() const { return ByValArgs.end(); } 397 byval_iterator byval_end() const { return ByValArgs.end(); }
386 398
397 llvm::CCAssignFn *fixedArgFn() const; 409 llvm::CCAssignFn *fixedArgFn() const;
398 410
399 /// Return the function that analyzes variable argument list functions. 411 /// Return the function that analyzes variable argument list functions.
400 llvm::CCAssignFn *varArgFn() const; 412 llvm::CCAssignFn *varArgFn() const;
401 413
402 const uint16_t *shadowRegs() const; 414 const MCPhysReg *shadowRegs() const;
403 415
404 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize, 416 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
405 unsigned Align); 417 unsigned Align);
406 418
407 /// Return the type of the register which is used to pass an argument or 419 /// Return the type of the register which is used to pass an argument or
424 protected: 436 protected:
425 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; 437 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
426 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; 438 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
427 439
428 // Subtarget Info 440 // Subtarget Info
429 const MipsSubtarget *Subtarget; 441 const MipsSubtarget &Subtarget;
430
431 bool HasMips64, IsN64, IsO32;
432 442
433 private: 443 private:
434 // Create a TargetGlobalAddress node. 444 // Create a TargetGlobalAddress node.
435 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 445 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
436 unsigned Flag) const; 446 unsigned Flag) const;
470 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 480 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
471 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const; 481 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
472 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 482 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
473 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const; 483 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
474 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 484 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
485 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
475 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 486 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
476 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const; 487 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
477 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 488 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
478 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 489 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
479 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 490 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
513 /// to the stack. Also create a stack frame object for the first variable 524 /// to the stack. Also create a stack frame object for the first variable
514 /// argument. 525 /// argument.
515 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC, 526 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
516 SDValue Chain, SDLoc DL, SelectionDAG &DAG) const; 527 SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
517 528
518 virtual SDValue 529 SDValue
519 LowerFormalArguments(SDValue Chain, 530 LowerFormalArguments(SDValue Chain,
520 CallingConv::ID CallConv, bool isVarArg, 531 CallingConv::ID CallConv, bool isVarArg,
521 const SmallVectorImpl<ISD::InputArg> &Ins, 532 const SmallVectorImpl<ISD::InputArg> &Ins,
522 SDLoc dl, SelectionDAG &DAG, 533 SDLoc dl, SelectionDAG &DAG,
523 SmallVectorImpl<SDValue> &InVals) const; 534 SmallVectorImpl<SDValue> &InVals) const override;
524 535
525 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain, 536 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
526 SDValue Arg, SDLoc DL, bool IsTailCall, 537 SDValue Arg, SDLoc DL, bool IsTailCall,
527 SelectionDAG &DAG) const; 538 SelectionDAG &DAG) const;
528 539
529 virtual SDValue 540 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
530 LowerCall(TargetLowering::CallLoweringInfo &CLI, 541 SmallVectorImpl<SDValue> &InVals) const override;
531 SmallVectorImpl<SDValue> &InVals) const; 542
532 543 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
533 virtual bool 544 bool isVarArg,
534 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 545 const SmallVectorImpl<ISD::OutputArg> &Outs,
535 bool isVarArg, 546 LLVMContext &Context) const override;
536 const SmallVectorImpl<ISD::OutputArg> &Outs, 547
537 LLVMContext &Context) const; 548 SDValue LowerReturn(SDValue Chain,
538 549 CallingConv::ID CallConv, bool isVarArg,
539 virtual SDValue 550 const SmallVectorImpl<ISD::OutputArg> &Outs,
540 LowerReturn(SDValue Chain, 551 const SmallVectorImpl<SDValue> &OutVals,
541 CallingConv::ID CallConv, bool isVarArg, 552 SDLoc dl, SelectionDAG &DAG) const override;
542 const SmallVectorImpl<ISD::OutputArg> &Outs,
543 const SmallVectorImpl<SDValue> &OutVals,
544 SDLoc dl, SelectionDAG &DAG) const;
545 553
546 // Inline asm support 554 // Inline asm support
547 ConstraintType getConstraintType(const std::string &Constraint) const; 555 ConstraintType
556 getConstraintType(const std::string &Constraint) const override;
548 557
549 /// Examine constraint string and operand type and determine a weight value. 558 /// Examine constraint string and operand type and determine a weight value.
550 /// The operand object must already have been set up with the operand type. 559 /// The operand object must already have been set up with the operand type.
551 ConstraintWeight getSingleConstraintMatchWeight( 560 ConstraintWeight getSingleConstraintMatchWeight(
552 AsmOperandInfo &info, const char *constraint) const; 561 AsmOperandInfo &info, const char *constraint) const override;
553 562
554 /// This function parses registers that appear in inline-asm constraints. 563 /// This function parses registers that appear in inline-asm constraints.
555 /// It returns pair (0, 0) on failure. 564 /// It returns pair (0, 0) on failure.
556 std::pair<unsigned, const TargetRegisterClass *> 565 std::pair<unsigned, const TargetRegisterClass *>
557 parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const; 566 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
558 567
559 std::pair<unsigned, const TargetRegisterClass*> 568 std::pair<unsigned, const TargetRegisterClass*>
560 getRegForInlineAsmConstraint(const std::string &Constraint, 569 getRegForInlineAsmConstraint(const std::string &Constraint,
561 MVT VT) const; 570 MVT VT) const override;
562 571
563 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 572 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
564 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 573 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
565 /// true it means one of the asm constraint of the inline asm instruction 574 /// true it means one of the asm constraint of the inline asm instruction
566 /// being processed is 'm'. 575 /// being processed is 'm'.
567 virtual void LowerAsmOperandForConstraint(SDValue Op, 576 void LowerAsmOperandForConstraint(SDValue Op,
568 std::string &Constraint, 577 std::string &Constraint,
569 std::vector<SDValue> &Ops, 578 std::vector<SDValue> &Ops,
570 SelectionDAG &DAG) const; 579 SelectionDAG &DAG) const override;
571 580
572 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const; 581 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
573 582
574 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 583 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
575 584
576 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 585 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
577 unsigned SrcAlign, 586 unsigned SrcAlign,
578 bool IsMemset, bool ZeroMemset, 587 bool IsMemset, bool ZeroMemset,
579 bool MemcpyStrSrc, 588 bool MemcpyStrSrc,
580 MachineFunction &MF) const; 589 MachineFunction &MF) const override;
581 590
582 /// isFPImmLegal - Returns true if the target can instruction select the 591 /// isFPImmLegal - Returns true if the target can instruction select the
583 /// specified FP immediate natively. If false, the legalizer will 592 /// specified FP immediate natively. If false, the legalizer will
584 /// materialize the FP immediate as a load from a constant pool. 593 /// materialize the FP immediate as a load from a constant pool.
585 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 594 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
586 595
587 virtual unsigned getJumpTableEncoding() const; 596 unsigned getJumpTableEncoding() const override;
597
598 /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
599 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr *MI,
600 MachineBasicBlock *BB,
601 unsigned Size, unsigned DstReg,
602 unsigned SrcRec) const;
588 603
589 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 604 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
590 unsigned Size, unsigned BinOpcode, bool Nand = false) const; 605 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
591 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI, 606 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
592 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, 607 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
593 bool Nand = false) const; 608 bool Nand = false) const;
594 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI, 609 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
595 MachineBasicBlock *BB, unsigned Size) const; 610 MachineBasicBlock *BB, unsigned Size) const;
596 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI, 611 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
597 MachineBasicBlock *BB, unsigned Size) const; 612 MachineBasicBlock *BB, unsigned Size) const;
613 MachineBasicBlock *emitSEL_D(MachineInstr *MI, MachineBasicBlock *BB) const;
598 }; 614 };
599 615
600 /// Create MipsTargetLowering objects. 616 /// Create MipsTargetLowering objects.
601 const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM); 617 const MipsTargetLowering *
602 const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM); 618 createMips16TargetLowering(MipsTargetMachine &TM, const MipsSubtarget &STI);
619 const MipsTargetLowering *
620 createMipsSETargetLowering(MipsTargetMachine &TM, const MipsSubtarget &STI);
621
622 namespace Mips {
623 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
624 const TargetLibraryInfo *libInfo);
625 }
603 } 626 }
604 627
605 #endif // MipsISELLOWERING_H 628 #endif