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comparison lib/Target/Mips/MipsInstrFPU.td @ 77:54457678186b LLVM3.6

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LLVM 3.6
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Mon, 08 Sep 2014 22:06:00 +0900
parents 95c75e76d11b
children 60c9769439b8
comparison
equal deleted inserted replaced
34:e874dbf0ad9d 77:54457678186b
55 55
56 //===----------------------------------------------------------------------===// 56 //===----------------------------------------------------------------------===//
57 // Feature predicates. 57 // Feature predicates.
58 //===----------------------------------------------------------------------===// 58 //===----------------------------------------------------------------------===//
59 59
60 def IsFP64bit : Predicate<"Subtarget.isFP64bit()">, 60 def IsFP64bit : Predicate<"Subtarget->isFP64bit()">,
61 AssemblerPredicate<"FeatureFP64Bit">; 61 AssemblerPredicate<"FeatureFP64Bit">;
62 def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">, 62 def NotFP64bit : Predicate<"!Subtarget->isFP64bit()">,
63 AssemblerPredicate<"!FeatureFP64Bit">; 63 AssemblerPredicate<"!FeatureFP64Bit">;
64 def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">, 64 def IsSingleFloat : Predicate<"Subtarget->isSingleFloat()">,
65 AssemblerPredicate<"FeatureSingleFloat">; 65 AssemblerPredicate<"FeatureSingleFloat">;
66 def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">, 66 def IsNotSingleFloat : Predicate<"!Subtarget->isSingleFloat()">,
67 AssemblerPredicate<"!FeatureSingleFloat">; 67 AssemblerPredicate<"!FeatureSingleFloat">;
68
69 //===----------------------------------------------------------------------===//
70 // Mips FGR size adjectives.
71 // They are mutually exclusive.
72 //===----------------------------------------------------------------------===//
73
74 class FGR_32 { list<Predicate> FGRPredicates = [NotFP64bit]; }
75 class FGR_64 { list<Predicate> FGRPredicates = [IsFP64bit]; }
76
77 //===----------------------------------------------------------------------===//
68 78
69 // FP immediate patterns. 79 // FP immediate patterns.
70 def fpimm0 : PatLeaf<(fpimm), [{ 80 def fpimm0 : PatLeaf<(fpimm), [{
71 return N->isExactlyValue(+0.0); 81 return N->isExactlyValue(+0.0);
72 }]>; 82 }]>;
91 101
92 class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm, 102 class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,
93 SDPatternOperator OpNode= null_frag> : 103 SDPatternOperator OpNode= null_frag> :
94 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft), 104 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
95 !strconcat(opstr, "\t$fd, $fs, $ft"), 105 !strconcat(opstr, "\t$fd, $fs, $ft"),
96 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR> { 106 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr> {
97 let isCommutable = IsComm; 107 let isCommutable = IsComm;
98 } 108 }
99 109
100 multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm, 110 multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
101 SDPatternOperator OpNode = null_frag> { 111 SDPatternOperator OpNode = null_frag> {
102 def _D32 : ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, 112 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>,
103 Requires<[NotFP64bit, HasStdEnc]>; 113 AdditionalRequires<[NotFP64bit]>;
104 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, 114 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin,
105 Requires<[IsFP64bit, HasStdEnc]> { 115 IsComm, OpNode>,
116 AdditionalRequires<[IsFP64bit]> {
106 string DecoderNamespace = "Mips64"; 117 string DecoderNamespace = "Mips64";
107 } 118 }
108 } 119 }
109 120
110 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 121 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
111 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 122 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
112 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"), 123 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
113 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR>, 124 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
114 NeverHasSideEffects; 125 NeverHasSideEffects;
115 126
116 multiclass ABSS_M<string opstr, InstrItinClass Itin, 127 multiclass ABSS_M<string opstr, InstrItinClass Itin,
117 SDPatternOperator OpNode= null_frag> { 128 SDPatternOperator OpNode= null_frag> {
118 def _D32 : ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>, 129 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
119 Requires<[NotFP64bit, HasStdEnc]>; 130 AdditionalRequires<[NotFP64bit]>;
120 def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, 131 def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
121 Requires<[IsFP64bit, HasStdEnc]> { 132 AdditionalRequires<[IsFP64bit]> {
122 string DecoderNamespace = "Mips64"; 133 string DecoderNamespace = "Mips64";
123 } 134 }
124 } 135 }
125 136
126 multiclass ROUND_M<string opstr, InstrItinClass Itin> { 137 multiclass ROUND_M<string opstr, InstrItinClass Itin> {
127 def _D32 : ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>, 138 def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>,
128 Requires<[NotFP64bit, HasStdEnc]>; 139 AdditionalRequires<[NotFP64bit]>;
129 def _D64 : ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>, 140 def _D64 : ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>,
130 Requires<[IsFP64bit, HasStdEnc]> { 141 AdditionalRequires<[IsFP64bit]> {
131 let DecoderNamespace = "Mips64"; 142 let DecoderNamespace = "Mips64";
132 } 143 }
133 } 144 }
134 145
135 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 146 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
136 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 147 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
137 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"), 148 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
138 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>; 149 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>;
139 150
140 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 151 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
141 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 152 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
142 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"), 153 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
143 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>; 154 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>;
155
156 class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
157 InstrItinClass Itin> :
158 InstSE<(outs DstRC:$fs), (ins DstRC:$fs_in, SrcRC:$rt),
159 !strconcat(opstr, "\t$rt, $fs"), [], Itin, FrmFR, opstr> {
160 // $fs_in is part of a white lie to work around a widespread bug in the FPU
161 // implementation. See expandBuildPairF64 for details.
162 let Constraints = "$fs = $fs_in";
163 }
144 164
145 class LW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 165 class LW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
146 SDPatternOperator OpNode= null_frag> : 166 SDPatternOperator OpNode= null_frag> :
147 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 167 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
148 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI> { 168 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
149 let DecoderMethod = "DecodeFMem"; 169 let DecoderMethod = "DecodeFMem";
150 let mayLoad = 1; 170 let mayLoad = 1;
151 } 171 }
152 172
153 class SW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 173 class SW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
154 SDPatternOperator OpNode= null_frag> : 174 SDPatternOperator OpNode= null_frag> :
155 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 175 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
156 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI> { 176 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
157 let DecoderMethod = "DecodeFMem"; 177 let DecoderMethod = "DecodeFMem";
158 let mayStore = 1; 178 let mayStore = 1;
159 } 179 }
160 180
161 class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 181 class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
162 SDPatternOperator OpNode = null_frag> : 182 SDPatternOperator OpNode = null_frag> :
163 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 183 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
164 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 184 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
165 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, FrmFR>; 185 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin,
186 FrmFR, opstr>;
166 187
167 class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 188 class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
168 SDPatternOperator OpNode = null_frag> : 189 SDPatternOperator OpNode = null_frag> :
169 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 190 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
170 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 191 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
171 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))], 192 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
172 Itin, FrmFR>; 193 Itin, FrmFR, opstr>;
173 194
174 class LWXC1_FT<string opstr, RegisterOperand DRC, 195 class LWXC1_FT<string opstr, RegisterOperand DRC,
175 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 196 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
176 InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index), 197 InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index),
177 !strconcat(opstr, "\t$fd, ${index}(${base})"), 198 !strconcat(opstr, "\t$fd, ${index}(${base})"),
178 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin, FrmFI> { 199 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin,
200 FrmFI, opstr> {
179 let AddedComplexity = 20; 201 let AddedComplexity = 20;
180 } 202 }
181 203
182 class SWXC1_FT<string opstr, RegisterOperand DRC, 204 class SWXC1_FT<string opstr, RegisterOperand DRC,
183 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 205 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
184 InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index), 206 InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index),
185 !strconcat(opstr, "\t$fs, ${index}(${base})"), 207 !strconcat(opstr, "\t$fs, ${index}(${base})"),
186 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin, FrmFI> { 208 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin,
209 FrmFI, opstr> {
187 let AddedComplexity = 20; 210 let AddedComplexity = 20;
188 } 211 }
189 212
190 class BC1F_FT<string opstr, InstrItinClass Itin, 213 class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
191 SDPatternOperator Op = null_frag> : 214 SDPatternOperator Op = null_frag> :
192 InstSE<(outs), (ins FCCRegsOpnd:$fcc, brtarget:$offset), 215 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
193 !strconcat(opstr, "\t$fcc, $offset"), 216 !strconcat(opstr, "\t$fcc, $offset"),
194 [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin, FrmFI> { 217 [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin,
218 FrmFI, opstr> {
195 let isBranch = 1; 219 let isBranch = 1;
196 let isTerminator = 1; 220 let isTerminator = 1;
197 let hasDelaySlot = 1; 221 let hasDelaySlot = 1;
198 let Defs = [AT]; 222 let Defs = [AT];
199 } 223 }
200 224
201 class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin, 225 class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
202 SDPatternOperator OpNode = null_frag> : 226 SDPatternOperator OpNode = null_frag> :
203 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond), 227 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
204 !strconcat("c.$cond.", typestr, "\t$fs, $ft"), 228 !strconcat("c.$cond.", typestr, "\t$fs, $ft"),
205 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR> { 229 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR,
230 !strconcat("c.$cond.", typestr)> {
206 let Defs = [FCC0]; 231 let Defs = [FCC0];
207 let isCodeGenOnly = 1; 232 let isCodeGenOnly = 1;
208 } 233 }
209 234
210 class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC> : 235 class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC,
236 InstrItinClass itin> :
211 InstSE<(outs), (ins RC:$fs, RC:$ft), 237 InstSE<(outs), (ins RC:$fs, RC:$ft),
212 !strconcat("c.", CondStr, ".", Typestr, "\t$fs, $ft"), [], IIFcmp, 238 !strconcat("c.", CondStr, ".", Typestr, "\t$fs, $ft"), [], itin,
213 FrmFR>; 239 FrmFR>;
214 240
215 multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt> { 241 multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt,
216 def C_F_#NAME : C_COND_FT<"f", TypeStr, RC>, C_COND_FM<fmt, 0>; 242 InstrItinClass itin> {
217 def C_UN_#NAME : C_COND_FT<"un", TypeStr, RC>, C_COND_FM<fmt, 1>; 243 def C_F_#NAME : C_COND_FT<"f", TypeStr, RC, itin>, C_COND_FM<fmt, 0>;
218 def C_EQ_#NAME : C_COND_FT<"eq", TypeStr, RC>, C_COND_FM<fmt, 2>; 244 def C_UN_#NAME : C_COND_FT<"un", TypeStr, RC, itin>, C_COND_FM<fmt, 1>;
219 def C_UEQ_#NAME : C_COND_FT<"ueq", TypeStr, RC>, C_COND_FM<fmt, 3>; 245 def C_EQ_#NAME : C_COND_FT<"eq", TypeStr, RC, itin>, C_COND_FM<fmt, 2>;
220 def C_OLT_#NAME : C_COND_FT<"olt", TypeStr, RC>, C_COND_FM<fmt, 4>; 246 def C_UEQ_#NAME : C_COND_FT<"ueq", TypeStr, RC, itin>, C_COND_FM<fmt, 3>;
221 def C_ULT_#NAME : C_COND_FT<"ult", TypeStr, RC>, C_COND_FM<fmt, 5>; 247 def C_OLT_#NAME : C_COND_FT<"olt", TypeStr, RC, itin>, C_COND_FM<fmt, 4>;
222 def C_OLE_#NAME : C_COND_FT<"ole", TypeStr, RC>, C_COND_FM<fmt, 6>; 248 def C_ULT_#NAME : C_COND_FT<"ult", TypeStr, RC, itin>, C_COND_FM<fmt, 5>;
223 def C_ULE_#NAME : C_COND_FT<"ule", TypeStr, RC>, C_COND_FM<fmt, 7>; 249 def C_OLE_#NAME : C_COND_FT<"ole", TypeStr, RC, itin>, C_COND_FM<fmt, 6>;
224 def C_SF_#NAME : C_COND_FT<"sf", TypeStr, RC>, C_COND_FM<fmt, 8>; 250 def C_ULE_#NAME : C_COND_FT<"ule", TypeStr, RC, itin>, C_COND_FM<fmt, 7>;
225 def C_NGLE_#NAME : C_COND_FT<"ngle", TypeStr, RC>, C_COND_FM<fmt, 9>; 251 def C_SF_#NAME : C_COND_FT<"sf", TypeStr, RC, itin>, C_COND_FM<fmt, 8>;
226 def C_SEQ_#NAME : C_COND_FT<"seq", TypeStr, RC>, C_COND_FM<fmt, 10>; 252 def C_NGLE_#NAME : C_COND_FT<"ngle", TypeStr, RC, itin>, C_COND_FM<fmt, 9>;
227 def C_NGL_#NAME : C_COND_FT<"ngl", TypeStr, RC>, C_COND_FM<fmt, 11>; 253 def C_SEQ_#NAME : C_COND_FT<"seq", TypeStr, RC, itin>, C_COND_FM<fmt, 10>;
228 def C_LT_#NAME : C_COND_FT<"lt", TypeStr, RC>, C_COND_FM<fmt, 12>; 254 def C_NGL_#NAME : C_COND_FT<"ngl", TypeStr, RC, itin>, C_COND_FM<fmt, 11>;
229 def C_NGE_#NAME : C_COND_FT<"nge", TypeStr, RC>, C_COND_FM<fmt, 13>; 255 def C_LT_#NAME : C_COND_FT<"lt", TypeStr, RC, itin>, C_COND_FM<fmt, 12>;
230 def C_LE_#NAME : C_COND_FT<"le", TypeStr, RC>, C_COND_FM<fmt, 14>; 256 def C_NGE_#NAME : C_COND_FT<"nge", TypeStr, RC, itin>, C_COND_FM<fmt, 13>;
231 def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC>, C_COND_FM<fmt, 15>; 257 def C_LE_#NAME : C_COND_FT<"le", TypeStr, RC, itin>, C_COND_FM<fmt, 14>;
232 } 258 def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC, itin>, C_COND_FM<fmt, 15>;
233 259 }
234 defm S : C_COND_M<"s", FGR32Opnd, 16>; 260
235 defm D32 : C_COND_M<"d", AFGR64Opnd, 17>, 261 defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6;
236 Requires<[NotFP64bit, HasStdEnc]>; 262 defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
263 AdditionalRequires<[NotFP64bit]>;
237 let DecoderNamespace = "Mips64" in 264 let DecoderNamespace = "Mips64" in
238 defm D64 : C_COND_M<"d", FGR64Opnd, 17>, Requires<[IsFP64bit, HasStdEnc]>; 265 defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
266 AdditionalRequires<[IsFP64bit]>;
239 267
240 //===----------------------------------------------------------------------===// 268 //===----------------------------------------------------------------------===//
241 // Floating Point Instructions 269 // Floating Point Instructions
242 //===----------------------------------------------------------------------===// 270 //===----------------------------------------------------------------------===//
243 def ROUND_W_S : ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>, 271 def ROUND_W_S : MMRel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
244 ABSS_FM<0xc, 16>; 272 ABSS_FM<0xc, 16>, ISA_MIPS2;
245 def TRUNC_W_S : ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>, 273 def TRUNC_W_S : MMRel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>,
246 ABSS_FM<0xd, 16>; 274 ABSS_FM<0xd, 16>, ISA_MIPS2;
247 def CEIL_W_S : ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>, 275 def CEIL_W_S : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
248 ABSS_FM<0xe, 16>; 276 ABSS_FM<0xe, 16>, ISA_MIPS2;
249 def FLOOR_W_S : ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>, 277 def FLOOR_W_S : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>,
250 ABSS_FM<0xf, 16>; 278 ABSS_FM<0xf, 16>, ISA_MIPS2;
251 def CVT_W_S : ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>, 279 def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
252 ABSS_FM<0x24, 16>; 280 ABSS_FM<0x24, 16>;
253 281
254 defm ROUND_W : ROUND_M<"round.w.d", IIFcvt>, ABSS_FM<0xc, 17>; 282 defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2;
255 defm TRUNC_W : ROUND_M<"trunc.w.d", IIFcvt>, ABSS_FM<0xd, 17>; 283 defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2;
256 defm CEIL_W : ROUND_M<"ceil.w.d", IIFcvt>, ABSS_FM<0xe, 17>; 284 defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2;
257 defm FLOOR_W : ROUND_M<"floor.w.d", IIFcvt>, ABSS_FM<0xf, 17>; 285 defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2;
258 defm CVT_W : ROUND_M<"cvt.w.d", IIFcvt>, ABSS_FM<0x24, 17>; 286 defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>;
259 287
260 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in { 288 let DecoderNamespace = "Mips64" in {
261 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>, 289 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>,
262 ABSS_FM<0x8, 16>; 290 ABSS_FM<0x8, 16>, FGR_64;
263 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>, 291 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>,
264 ABSS_FM<0x8, 17>; 292 ABSS_FM<0x8, 17>, FGR_64;
265 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>, 293 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>,
266 ABSS_FM<0x9, 16>; 294 ABSS_FM<0x9, 16>, FGR_64;
267 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>, 295 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>,
268 ABSS_FM<0x9, 17>; 296 ABSS_FM<0x9, 17>, FGR_64;
269 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>, 297 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, II_CEIL>,
270 ABSS_FM<0xa, 16>; 298 ABSS_FM<0xa, 16>, FGR_64;
271 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>, 299 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, II_CEIL>,
272 ABSS_FM<0xa, 17>; 300 ABSS_FM<0xa, 17>, FGR_64;
273 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>, 301 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>,
274 ABSS_FM<0xb, 16>; 302 ABSS_FM<0xb, 16>, FGR_64;
275 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>, 303 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>,
276 ABSS_FM<0xb, 17>; 304 ABSS_FM<0xb, 17>, FGR_64;
277 } 305 }
278 306
279 def CVT_S_W : ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, IIFcvt>, 307 def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
280 ABSS_FM<0x20, 20>; 308 ABSS_FM<0x20, 20>;
281 def CVT_L_S : ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>, 309 def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
282 ABSS_FM<0x25, 16>; 310 ABSS_FM<0x25, 16>, INSN_MIPS3_32R2;
283 def CVT_L_D64: ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>, 311 def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
284 ABSS_FM<0x25, 17>; 312 ABSS_FM<0x25, 17>, INSN_MIPS3_32R2;
285 313
286 let Predicates = [NotFP64bit, HasStdEnc] in { 314 def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
287 def CVT_S_D32 : ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, IIFcvt>, 315 ABSS_FM<0x20, 17>, FGR_32;
288 ABSS_FM<0x20, 17>; 316 def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
289 def CVT_D32_W : ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, IIFcvt>, 317 ABSS_FM<0x21, 20>, FGR_32;
290 ABSS_FM<0x21, 20>; 318 def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
291 def CVT_D32_S : ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, IIFcvt>, 319 ABSS_FM<0x21, 16>, FGR_32;
292 ABSS_FM<0x21, 16>; 320
293 } 321 let DecoderNamespace = "Mips64" in {
294 322 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
295 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in { 323 ABSS_FM<0x20, 17>, FGR_64;
296 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, IIFcvt>, 324 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>,
297 ABSS_FM<0x20, 17>; 325 ABSS_FM<0x20, 21>, FGR_64;
298 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, IIFcvt>, 326 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>,
299 ABSS_FM<0x20, 21>; 327 ABSS_FM<0x21, 20>, FGR_64;
300 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, IIFcvt>, 328 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>,
301 ABSS_FM<0x21, 20>; 329 ABSS_FM<0x21, 16>, FGR_64;
302 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, IIFcvt>, 330 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>,
303 ABSS_FM<0x21, 16>; 331 ABSS_FM<0x21, 21>, FGR_64;
304 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, IIFcvt>,
305 ABSS_FM<0x21, 21>;
306 } 332 }
307 333
308 let isPseudo = 1, isCodeGenOnly = 1 in { 334 let isPseudo = 1, isCodeGenOnly = 1 in {
309 def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, IIFcvt>; 335 def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>;
310 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, IIFcvt>; 336 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>;
311 def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, IIFcvt>; 337 def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
312 def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, IIFcvt>; 338 def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>;
313 def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, IIFcvt>; 339 def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
314 } 340 }
315 341
316 let Predicates = [NoNaNsFPMath, HasStdEnc] in { 342 def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
317 def FABS_S : ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, IIFcvt, fabs>, 343 ABSS_FM<0x5, 16>;
318 ABSS_FM<0x5, 16>; 344 def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
319 def FNEG_S : ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, IIFcvt, fneg>, 345 ABSS_FM<0x7, 16>;
320 ABSS_FM<0x7, 16>; 346 defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>;
321 defm FABS : ABSS_M<"abs.d", IIFcvt, fabs>, ABSS_FM<0x5, 17>; 347 defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>;
322 defm FNEG : ABSS_M<"neg.d", IIFcvt, fneg>, ABSS_FM<0x7, 17>; 348
323 } 349 def FSQRT_S : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, fsqrt>,
324 350 ABSS_FM<0x4, 16>, ISA_MIPS2;
325 def FSQRT_S : ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, IIFsqrtSingle, 351 defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
326 fsqrt>, ABSS_FM<0x4, 16>;
327 defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>;
328 352
329 // The odd-numbered registers are only referenced when doing loads, 353 // The odd-numbered registers are only referenced when doing loads,
330 // stores, and moves between floating-point and integer registers. 354 // stores, and moves between floating-point and integer registers.
331 // When defining instructions, we reference all 32-bit registers, 355 // When defining instructions, we reference all 32-bit registers,
332 // regardless of register aliasing. 356 // regardless of register aliasing.
333 357
334 /// Move Control Registers From/To CPU Registers 358 /// Move Control Registers From/To CPU Registers
335 def CFC1 : MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, IIFmove>, MFC1_FM<2>; 359 def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>;
336 def CTC1 : MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, IIFmove>, MFC1_FM<6>; 360 def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>;
337 def MFC1 : MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, IIFmoveC1, bitconvert>, 361 def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
338 MFC1_FM<0>; 362 bitconvert>, MFC1_FM<0>;
339 def MTC1 : MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, IIFmoveC1, bitconvert>, 363 def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
340 MFC1_FM<4>; 364 bitconvert>, MFC1_FM<4>;
341 def MFHC1 : MFC1_FT<"mfhc1", GPR32Opnd, FGRH32Opnd, IIFmoveC1>, 365 def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
342 MFC1_FM<3>; 366 MFC1_FM<3>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>;
343 def MTHC1 : MTC1_FT<"mthc1", FGRH32Opnd, GPR32Opnd, IIFmoveC1>, 367 def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>,
344 MFC1_FM<7>; 368 MFC1_FM<3>, ISA_MIPS32R2, AdditionalRequires<[IsFP64bit]> {
345 def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, IIFmoveC1, 369 let DecoderNamespace = "Mips64";
346 bitconvert>, MFC1_FM<1>; 370 }
347 def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, IIFmoveC1, 371 def MTHC1_D32 : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
348 bitconvert>, MFC1_FM<5>; 372 MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>;
349 373 def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
350 def FMOV_S : ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, IIFmove>, 374 MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[IsFP64bit]> {
375 let DecoderNamespace = "Mips64";
376 }
377 def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,
378 bitconvert>, MFC1_FM<1>, ISA_MIPS3;
379 def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1,
380 bitconvert>, MFC1_FM<5>, ISA_MIPS3;
381
382 def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
351 ABSS_FM<0x6, 16>; 383 ABSS_FM<0x6, 16>;
352 def FMOV_D32 : ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, IIFmove>, 384 def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
353 ABSS_FM<0x6, 17>, Requires<[NotFP64bit, HasStdEnc]>; 385 ABSS_FM<0x6, 17>, AdditionalRequires<[NotFP64bit]>;
354 def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, IIFmove>, 386 def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>,
355 ABSS_FM<0x6, 17>, Requires<[IsFP64bit, HasStdEnc]> { 387 ABSS_FM<0x6, 17>, AdditionalRequires<[IsFP64bit]> {
356 let DecoderNamespace = "Mips64"; 388 let DecoderNamespace = "Mips64";
357 } 389 }
358 390
359 /// Floating Point Memory Instructions 391 /// Floating Point Memory Instructions
360 let Predicates = [HasStdEnc] in { 392 def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM<0x31>;
361 def LWC1 : LW_FT<"lwc1", FGR32Opnd, IIFLoad, load>, LW_FM<0x31>; 393 def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM<0x39>;
362 def SWC1 : SW_FT<"swc1", FGR32Opnd, IIFStore, store>, LW_FM<0x39>; 394
363 } 395 let DecoderNamespace = "Mips64" in {
364 396 def LDC164 : LW_FT<"ldc1", FGR64Opnd, II_LDC1, load>, LW_FM<0x35>, ISA_MIPS2,
365 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in { 397 FGR_64;
366 def LDC164 : LW_FT<"ldc1", FGR64Opnd, IIFLoad, load>, LW_FM<0x35>; 398 def SDC164 : SW_FT<"sdc1", FGR64Opnd, II_SDC1, store>, LW_FM<0x3d>, ISA_MIPS2,
367 def SDC164 : SW_FT<"sdc1", FGR64Opnd, IIFStore, store>, LW_FM<0x3d>; 399 FGR_64;
368 } 400 }
369 401
370 let Predicates = [NotFP64bit, HasStdEnc] in { 402 def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>,
371 def LDC1 : LW_FT<"ldc1", AFGR64Opnd, IIFLoad, load>, LW_FM<0x35>; 403 ISA_MIPS2, FGR_32;
372 def SDC1 : SW_FT<"sdc1", AFGR64Opnd, IIFStore, store>, LW_FM<0x3d>; 404 def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>,
373 } 405 ISA_MIPS2, FGR_32;
374 406
375 /// Cop2 Memory Instructions 407 // Cop2 Memory Instructions
376 let Predicates = [HasStdEnc] in { 408 // FIXME: These aren't really FPU instructions and as such don't belong in this
377 def LWC2 : LW_FT<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>; 409 // file
378 def SWC2 : SW_FT<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>; 410 def LWC2 : LW_FT<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
379 def LDC2 : LW_FT<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>; 411 ISA_MIPS1_NOT_32R6_64R6;
380 def SDC2 : SW_FT<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>; 412 def SWC2 : SW_FT<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
413 ISA_MIPS1_NOT_32R6_64R6;
414 def LDC2 : LW_FT<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
415 ISA_MIPS2_NOT_32R6_64R6;
416 def SDC2 : SW_FT<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
417 ISA_MIPS2_NOT_32R6_64R6;
418
419 // Cop3 Memory Instructions
420 // FIXME: These aren't really FPU instructions and as such don't belong in this
421 // file
422 let DecoderNamespace = "COP3_" in {
423 def LWC3 : LW_FT<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
424 def SWC3 : SW_FT<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
425 def LDC3 : LW_FT<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>,
426 ISA_MIPS2;
427 def SDC3 : SW_FT<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
428 ISA_MIPS2;
381 } 429 }
382 430
383 // Indexed loads and stores. 431 // Indexed loads and stores.
384 let Predicates = [HasFPIdx, HasStdEnc] in { 432 // Base register + offset register addressing mode (indicated by "x" in the
385 def LWXC1 : LWXC1_FT<"lwxc1", FGR32Opnd, IIFLoad, load>, LWXC1_FM<0>; 433 // instruction mnemonic) is disallowed under NaCl.
386 def SWXC1 : SWXC1_FT<"swxc1", FGR32Opnd, IIFStore, store>, SWXC1_FM<8>; 434 let AdditionalPredicates = [IsNotNaCl] in {
387 } 435 def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>,
388 436 INSN_MIPS4_32R2_NOT_32R6_64R6;
389 let Predicates = [HasFPIdx, NotFP64bit, HasStdEnc] in { 437 def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>,
390 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, IIFLoad, load>, LWXC1_FM<1>; 438 INSN_MIPS4_32R2_NOT_32R6_64R6;
391 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, IIFStore, store>, SWXC1_FM<9>; 439 }
392 } 440
393 441 let AdditionalPredicates = [NotInMicroMips, IsNotNaCl] in {
394 let Predicates = [HasFPIdx, IsFP64bit, HasStdEnc], 442 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
395 DecoderNamespace="Mips64" in { 443 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
396 def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, IIFLoad, load>, LWXC1_FM<1>; 444 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
397 def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, IIFStore, store>, SWXC1_FM<9>; 445 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
446 }
447
448 let DecoderNamespace="Mips64" in {
449 def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
450 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
451 def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
452 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
398 } 453 }
399 454
400 // Load/store doubleword indexed unaligned. 455 // Load/store doubleword indexed unaligned.
401 let Predicates = [NotFP64bit, HasStdEnc] in { 456 let AdditionalPredicates = [IsNotNaCl] in {
402 def LUXC1 : LWXC1_FT<"luxc1", AFGR64Opnd, IIFLoad>, LWXC1_FM<0x5>; 457 def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
403 def SUXC1 : SWXC1_FT<"suxc1", AFGR64Opnd, IIFStore>, SWXC1_FM<0xd>; 458 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
404 } 459 def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
405 460 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
406 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace="Mips64" in { 461 }
407 def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, IIFLoad>, LWXC1_FM<0x5>; 462
408 def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, IIFStore>, SWXC1_FM<0xd>; 463 let DecoderNamespace="Mips64" in {
464 def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
465 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
466 def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
467 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
409 } 468 }
410 469
411 /// Floating-point Aritmetic 470 /// Floating-point Aritmetic
412 def FADD_S : ADDS_FT<"add.s", FGR32Opnd, IIFadd, 1, fadd>, 471 def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,
413 ADDS_FM<0x00, 16>; 472 ADDS_FM<0x00, 16>;
414 defm FADD : ADDS_M<"add.d", IIFadd, 1, fadd>, ADDS_FM<0x00, 17>; 473 defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>;
415 def FDIV_S : ADDS_FT<"div.s", FGR32Opnd, IIFdivSingle, 0, fdiv>, 474 def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
416 ADDS_FM<0x03, 16>; 475 ADDS_FM<0x03, 16>;
417 defm FDIV : ADDS_M<"div.d", IIFdivDouble, 0, fdiv>, ADDS_FM<0x03, 17>; 476 defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>;
418 def FMUL_S : ADDS_FT<"mul.s", FGR32Opnd, IIFmulSingle, 1, fmul>, 477 def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
419 ADDS_FM<0x02, 16>; 478 ADDS_FM<0x02, 16>;
420 defm FMUL : ADDS_M<"mul.d", IIFmulDouble, 1, fmul>, ADDS_FM<0x02, 17>; 479 defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>;
421 def FSUB_S : ADDS_FT<"sub.s", FGR32Opnd, IIFadd, 0, fsub>, 480 def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
422 ADDS_FM<0x01, 16>; 481 ADDS_FM<0x01, 16>;
423 defm FSUB : ADDS_M<"sub.d", IIFadd, 0, fsub>, ADDS_FM<0x01, 17>; 482 defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>;
424 483
425 let Predicates = [HasMips32r2, HasStdEnc] in { 484 def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
426 def MADD_S : MADDS_FT<"madd.s", FGR32Opnd, IIFmulSingle, fadd>, 485 MADDS_FM<4, 0>, ISA_MIPS32R2_NOT_32R6_64R6;
427 MADDS_FM<4, 0>; 486 def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
428 def MSUB_S : MADDS_FT<"msub.s", FGR32Opnd, IIFmulSingle, fsub>, 487 MADDS_FM<5, 0>, ISA_MIPS32R2_NOT_32R6_64R6;
429 MADDS_FM<5, 0>; 488
430 } 489 let AdditionalPredicates = [NoNaNsFPMath] in {
431 490 def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
432 let Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in { 491 MADDS_FM<6, 0>, ISA_MIPS32R2_NOT_32R6_64R6;
433 def NMADD_S : NMADDS_FT<"nmadd.s", FGR32Opnd, IIFmulSingle, fadd>, 492 def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
434 MADDS_FM<6, 0>; 493 MADDS_FM<7, 0>, ISA_MIPS32R2_NOT_32R6_64R6;
435 def NMSUB_S : NMADDS_FT<"nmsub.s", FGR32Opnd, IIFmulSingle, fsub>, 494 }
436 MADDS_FM<7, 0>; 495
437 } 496 def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
438 497 MADDS_FM<4, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32;
439 let Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in { 498 def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
440 def MADD_D32 : MADDS_FT<"madd.d", AFGR64Opnd, IIFmulDouble, fadd>, 499 MADDS_FM<5, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32;
441 MADDS_FM<4, 1>; 500
442 def MSUB_D32 : MADDS_FT<"msub.d", AFGR64Opnd, IIFmulDouble, fsub>, 501 let AdditionalPredicates = [NoNaNsFPMath] in {
443 MADDS_FM<5, 1>; 502 def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
444 } 503 MADDS_FM<6, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32;
445 504 def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
446 let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in { 505 MADDS_FM<7, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32;
447 def NMADD_D32 : NMADDS_FT<"nmadd.d", AFGR64Opnd, IIFmulDouble, fadd>, 506 }
448 MADDS_FM<6, 1>; 507
449 def NMSUB_D32 : NMADDS_FT<"nmsub.d", AFGR64Opnd, IIFmulDouble, fsub>, 508 let isCodeGenOnly=1 in {
450 MADDS_FM<7, 1>; 509 def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
451 } 510 MADDS_FM<4, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
452 511 def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
453 let Predicates = [HasMips32r2, IsFP64bit, HasStdEnc], isCodeGenOnly=1 in { 512 MADDS_FM<5, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
454 def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, IIFmulDouble, fadd>, 513 }
455 MADDS_FM<4, 1>; 514
456 def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, IIFmulDouble, fsub>, 515 let AdditionalPredicates = [NoNaNsFPMath],
457 MADDS_FM<5, 1>;
458 }
459
460 let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc],
461 isCodeGenOnly=1 in { 516 isCodeGenOnly=1 in {
462 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, IIFmulDouble, fadd>, 517 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>,
463 MADDS_FM<6, 1>; 518 MADDS_FM<6, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
464 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, IIFmulDouble, fsub>, 519 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>,
465 MADDS_FM<7, 1>; 520 MADDS_FM<7, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
466 } 521 }
467 522
468 //===----------------------------------------------------------------------===// 523 //===----------------------------------------------------------------------===//
469 // Floating Point Branch Codes 524 // Floating Point Branch Codes
470 //===----------------------------------------------------------------------===// 525 //===----------------------------------------------------------------------===//
471 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h. 526 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
472 // They must be kept in synch. 527 // They must be kept in synch.
473 def MIPS_BRANCH_F : PatLeaf<(i32 0)>; 528 def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
474 def MIPS_BRANCH_T : PatLeaf<(i32 1)>; 529 def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
475 530
476 def BC1F : BC1F_FT<"bc1f", IIBranch, MIPS_BRANCH_F>, BC1F_FM<0, 0>; 531 def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, IIBranch, MIPS_BRANCH_F>,
477 def BC1T : BC1F_FT<"bc1t", IIBranch, MIPS_BRANCH_T>, BC1F_FM<0, 1>; 532 BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
533 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, IIBranch, MIPS_BRANCH_T>,
534 BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;
478 535
479 //===----------------------------------------------------------------------===// 536 //===----------------------------------------------------------------------===//
480 // Floating Point Flag Conditions 537 // Floating Point Flag Conditions
481 //===----------------------------------------------------------------------===// 538 //===----------------------------------------------------------------------===//
482 // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h. 539 // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
497 def MIPS_FCOND_NGE : PatLeaf<(i32 13)>; 554 def MIPS_FCOND_NGE : PatLeaf<(i32 13)>;
498 def MIPS_FCOND_LE : PatLeaf<(i32 14)>; 555 def MIPS_FCOND_LE : PatLeaf<(i32 14)>;
499 def MIPS_FCOND_NGT : PatLeaf<(i32 15)>; 556 def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
500 557
501 /// Floating Point Compare 558 /// Floating Point Compare
502 def FCMP_S32 : CEQS_FT<"s", FGR32, IIFcmp, MipsFPCmp>, CEQS_FM<16>; 559 def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>,
503 def FCMP_D32 : CEQS_FT<"d", AFGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>, 560 ISA_MIPS1_NOT_32R6_64R6;
504 Requires<[NotFP64bit, HasStdEnc]>; 561 def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
562 ISA_MIPS1_NOT_32R6_64R6, AdditionalRequires<[NotFP64bit]>;
505 let DecoderNamespace = "Mips64" in 563 let DecoderNamespace = "Mips64" in
506 def FCMP_D64 : CEQS_FT<"d", FGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>, 564 def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
507 Requires<[IsFP64bit, HasStdEnc]>; 565 ISA_MIPS1_NOT_32R6_64R6, AdditionalRequires<[IsFP64bit]>;
508 566
509 //===----------------------------------------------------------------------===// 567 //===----------------------------------------------------------------------===//
510 // Floating Point Pseudo-Instructions 568 // Floating Point Pseudo-Instructions
511 //===----------------------------------------------------------------------===// 569 //===----------------------------------------------------------------------===//
512 570
515 class BuildPairF64Base<RegisterOperand RO> : 573 class BuildPairF64Base<RegisterOperand RO> :
516 PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi), 574 PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi),
517 [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))]>; 575 [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))]>;
518 576
519 def BuildPairF64 : BuildPairF64Base<AFGR64Opnd>, 577 def BuildPairF64 : BuildPairF64Base<AFGR64Opnd>,
520 Requires<[NotFP64bit, HasStdEnc]>; 578 AdditionalRequires<[NotFP64bit]>;
521 def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>, 579 def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>,
522 Requires<[IsFP64bit, HasStdEnc]>; 580 AdditionalRequires<[IsFP64bit]>;
523 581
524 // This pseudo instr gets expanded into 2 mfc1 instrs after register 582 // This pseudo instr gets expanded into 2 mfc1 instrs after register
525 // allocation. 583 // allocation.
526 // if n is 0, lower part of src is extracted. 584 // if n is 0, lower part of src is extracted.
527 // if n is 1, higher part of src is extracted. 585 // if n is 1, higher part of src is extracted.
528 class ExtractElementF64Base<RegisterOperand RO> : 586 class ExtractElementF64Base<RegisterOperand RO> :
529 PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n), 587 PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n),
530 [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))]>; 588 [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))]>;
531 589
532 def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>, 590 def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>,
533 Requires<[NotFP64bit, HasStdEnc]>; 591 AdditionalRequires<[NotFP64bit]>;
534 def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>, 592 def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>,
535 Requires<[IsFP64bit, HasStdEnc]>; 593 AdditionalRequires<[IsFP64bit]>;
536 594
537 //===----------------------------------------------------------------------===// 595 //===----------------------------------------------------------------------===//
538 // InstAliases. 596 // InstAliases.
539 //===----------------------------------------------------------------------===// 597 //===----------------------------------------------------------------------===//
540 def : InstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>; 598 def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>,
541 def : InstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>; 599 ISA_MIPS1_NOT_32R6_64R6;
600 def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>,
601 ISA_MIPS1_NOT_32R6_64R6;
542 602
543 //===----------------------------------------------------------------------===// 603 //===----------------------------------------------------------------------===//
544 // Floating Point Patterns 604 // Floating Point Patterns
545 //===----------------------------------------------------------------------===// 605 //===----------------------------------------------------------------------===//
546 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>; 606 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
549 def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)), 609 def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)),
550 (PseudoCVT_S_W GPR32Opnd:$src)>; 610 (PseudoCVT_S_W GPR32Opnd:$src)>;
551 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), 611 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
552 (TRUNC_W_S FGR32Opnd:$src)>; 612 (TRUNC_W_S FGR32Opnd:$src)>;
553 613
554 let Predicates = [NotFP64bit, HasStdEnc] in { 614 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
555 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), 615 (PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32;
556 (PseudoCVT_D32_W GPR32Opnd:$src)>; 616 def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),
557 def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src), 617 (TRUNC_W_D32 AFGR64Opnd:$src)>, FGR_32;
558 (TRUNC_W_D32 AFGR64Opnd:$src)>; 618 def : MipsPat<(f32 (fround AFGR64Opnd:$src)),
559 def : MipsPat<(f32 (fround AFGR64Opnd:$src)), 619 (CVT_S_D32 AFGR64Opnd:$src)>, FGR_32;
560 (CVT_S_D32 AFGR64Opnd:$src)>; 620 def : MipsPat<(f64 (fextend FGR32Opnd:$src)),
561 def : MipsPat<(f64 (fextend FGR32Opnd:$src)), 621 (CVT_D32_S FGR32Opnd:$src)>, FGR_32;
562 (CVT_D32_S FGR32Opnd:$src)>; 622
563 } 623 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, FGR_64;
564 624 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, FGR_64;
565 let Predicates = [IsFP64bit, HasStdEnc] in { 625
566 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>; 626 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
567 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>; 627 (PseudoCVT_D64_W GPR32Opnd:$src)>, FGR_64;
568 628 def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)),
569 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), 629 (EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>, FGR_64;
570 (PseudoCVT_D64_W GPR32Opnd:$src)>; 630 def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)),
571 def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)), 631 (PseudoCVT_D64_L GPR64Opnd:$src)>, FGR_64;
572 (EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>; 632
573 def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)), 633 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
574 (PseudoCVT_D64_L GPR64Opnd:$src)>; 634 (TRUNC_W_D64 FGR64Opnd:$src)>, FGR_64;
575 635 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
576 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), 636 (TRUNC_L_S FGR32Opnd:$src)>, FGR_64;
577 (TRUNC_W_D64 FGR64Opnd:$src)>; 637 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
578 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), 638 (TRUNC_L_D64 FGR64Opnd:$src)>, FGR_64;
579 (TRUNC_L_S FGR32Opnd:$src)>; 639
580 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), 640 def : MipsPat<(f32 (fround FGR64Opnd:$src)),
581 (TRUNC_L_D64 FGR64Opnd:$src)>; 641 (CVT_S_D64 FGR64Opnd:$src)>, FGR_64;
582 642 def : MipsPat<(f64 (fextend FGR32Opnd:$src)),
583 def : MipsPat<(f32 (fround FGR64Opnd:$src)), 643 (CVT_D64_S FGR32Opnd:$src)>, FGR_64;
584 (CVT_S_D64 FGR64Opnd:$src)>;
585 def : MipsPat<(f64 (fextend FGR32Opnd:$src)),
586 (CVT_D64_S FGR32Opnd:$src)>;
587 }
588 644
589 // Patterns for loads/stores with a reg+imm operand. 645 // Patterns for loads/stores with a reg+imm operand.
590 let AddedComplexity = 40 in { 646 let AddedComplexity = 40 in {
591 let Predicates = [HasStdEnc] in { 647 def : LoadRegImmPat<LWC1, f32, load>;
592 def : LoadRegImmPat<LWC1, f32, load>; 648 def : StoreRegImmPat<SWC1, f32>;
593 def : StoreRegImmPat<SWC1, f32>; 649
594 } 650 def : LoadRegImmPat<LDC164, f64, load>, FGR_64;
595 651 def : StoreRegImmPat<SDC164, f64>, FGR_64;
596 let Predicates = [IsFP64bit, HasStdEnc] in { 652
597 def : LoadRegImmPat<LDC164, f64, load>; 653 def : LoadRegImmPat<LDC1, f64, load>, FGR_32;
598 def : StoreRegImmPat<SDC164, f64>; 654 def : StoreRegImmPat<SDC1, f64>, FGR_32;
599 } 655 }
600
601 let Predicates = [NotFP64bit, HasStdEnc] in {
602 def : LoadRegImmPat<LDC1, f64, load>;
603 def : StoreRegImmPat<SDC1, f64>;
604 }
605 }