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comparison lib/Target/Mips/MipsSEISelDAGToDAG.cpp @ 77:54457678186b LLVM3.6

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LLVM 3.6
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Mon, 08 Sep 2014 22:06:00 +0900
parents 95c75e76d11b
children 60c9769439b8
comparison
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34:e874dbf0ad9d 77:54457678186b
9 // 9 //
10 // Subclass of MipsDAGToDAGISel specialized for mips32/64. 10 // Subclass of MipsDAGToDAGISel specialized for mips32/64.
11 // 11 //
12 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===//
13 13
14 #define DEBUG_TYPE "mips-isel"
15 #include "MipsSEISelDAGToDAG.h" 14 #include "MipsSEISelDAGToDAG.h"
15 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "Mips.h" 16 #include "Mips.h"
17 #include "MCTargetDesc/MipsBaseInfo.h"
18 #include "MipsAnalyzeImmediate.h" 17 #include "MipsAnalyzeImmediate.h"
19 #include "MipsMachineFunction.h" 18 #include "MipsMachineFunction.h"
20 #include "MipsRegisterInfo.h" 19 #include "MipsRegisterInfo.h"
21 #include "llvm/CodeGen/MachineConstantPool.h" 20 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h" 24 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGNodes.h" 25 #include "llvm/CodeGen/SelectionDAGNodes.h"
26 #include "llvm/IR/CFG.h"
27 #include "llvm/IR/GlobalValue.h" 27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Instructions.h" 28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h" 29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h" 30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/CFG.h"
32 #include "llvm/Support/Debug.h" 31 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h" 32 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h" 33 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetMachine.h" 34 #include "llvm/Target/TargetMachine.h"
36 using namespace llvm; 35 using namespace llvm;
37 36
37 #define DEBUG_TYPE "mips-isel"
38
38 bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { 39 bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
39 if (Subtarget.inMips16Mode()) 40 Subtarget = &TM.getSubtarget<MipsSubtarget>();
41 if (Subtarget->inMips16Mode())
40 return false; 42 return false;
41 return MipsDAGToDAGISel::runOnMachineFunction(MF); 43 return MipsDAGToDAGISel::runOnMachineFunction(MF);
42 } 44 }
43 45
44 void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI, 46 void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
102 return false; 104 return false;
103 105
104 // Replace uses with ZeroReg. 106 // Replace uses with ZeroReg.
105 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg), 107 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
106 E = MRI->use_end(); U != E;) { 108 E = MRI->use_end(); U != E;) {
107 MachineOperand &MO = U.getOperand(); 109 MachineOperand &MO = *U;
108 unsigned OpNo = U.getOperandNo(); 110 unsigned OpNo = U.getOperandNo();
109 MachineInstr *MI = MO.getParent(); 111 MachineInstr *MI = MO.getParent();
110 ++U; 112 ++U;
111 113
112 // Do not replace if it is a phi's operand or is tied to def operand. 114 // Do not replace if it is a phi's operand or is tied to def operand.
126 return; 128 return;
127 129
128 MachineBasicBlock &MBB = MF.front(); 130 MachineBasicBlock &MBB = MF.front();
129 MachineBasicBlock::iterator I = MBB.begin(); 131 MachineBasicBlock::iterator I = MBB.begin();
130 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 132 MachineRegisterInfo &RegInfo = MF.getRegInfo();
131 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 133 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
132 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); 134 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
133 unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg(); 135 unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
134 const TargetRegisterClass *RC; 136 const TargetRegisterClass *RC;
135 137
136 if (Subtarget.isABI_N64()) 138 if (Subtarget->isABI_N64())
137 RC = (const TargetRegisterClass*)&Mips::GPR64RegClass; 139 RC = (const TargetRegisterClass*)&Mips::GPR64RegClass;
138 else 140 else
139 RC = (const TargetRegisterClass*)&Mips::GPR32RegClass; 141 RC = (const TargetRegisterClass*)&Mips::GPR32RegClass;
140 142
141 V0 = RegInfo.createVirtualRegister(RC); 143 V0 = RegInfo.createVirtualRegister(RC);
142 V1 = RegInfo.createVirtualRegister(RC); 144 V1 = RegInfo.createVirtualRegister(RC);
143 145
144 if (Subtarget.isABI_N64()) { 146 if (Subtarget->isABI_N64()) {
145 MF.getRegInfo().addLiveIn(Mips::T9_64); 147 MF.getRegInfo().addLiveIn(Mips::T9_64);
146 MBB.addLiveIn(Mips::T9_64); 148 MBB.addLiveIn(Mips::T9_64);
147 149
148 // lui $v0, %hi(%neg(%gp_rel(fname))) 150 // lui $v0, %hi(%neg(%gp_rel(fname)))
149 // daddu $v1, $v0, $t9 151 // daddu $v1, $v0, $t9
171 } 173 }
172 174
173 MF.getRegInfo().addLiveIn(Mips::T9); 175 MF.getRegInfo().addLiveIn(Mips::T9);
174 MBB.addLiveIn(Mips::T9); 176 MBB.addLiveIn(Mips::T9);
175 177
176 if (Subtarget.isABI_N32()) { 178 if (Subtarget->isABI_N32()) {
177 // lui $v0, %hi(%neg(%gp_rel(fname))) 179 // lui $v0, %hi(%neg(%gp_rel(fname)))
178 // addu $v1, $v0, $t9 180 // addu $v1, $v0, $t9
179 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname))) 181 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
180 const GlobalValue *FName = MF.getFunction(); 182 const GlobalValue *FName = MF.getFunction();
181 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) 183 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
184 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1) 186 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
185 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO); 187 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
186 return; 188 return;
187 } 189 }
188 190
189 assert(Subtarget.isABI_O32()); 191 assert(Subtarget->isABI_O32());
190 192
191 // For O32 ABI, the following instruction sequence is emitted to initialize 193 // For O32 ABI, the following instruction sequence is emitted to initialize
192 // the global base register: 194 // the global base register:
193 // 195 //
194 // 0. lui $2, %hi(_gp_disp) 196 // 0. lui $2, %hi(_gp_disp)
246 SDValue(Carry, 0), RHS); 248 SDValue(Carry, 0), RHS);
247 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS, 249 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
248 SDValue(AddCarry, 0)); 250 SDValue(AddCarry, 0));
249 } 251 }
250 252
251 /// ComplexPattern used on MipsInstrInfo 253 /// Match frameindex
252 /// Used on Mips Load/Store instructions 254 bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
253 bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base, 255 SDValue &Offset) const {
254 SDValue &Offset) const {
255 EVT ValTy = Addr.getValueType();
256
257 // if Address is FI, get the TargetFrameIndex.
258 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 256 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
257 EVT ValTy = Addr.getValueType();
258
259 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); 259 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
260 Offset = CurDAG->getTargetConstant(0, ValTy); 260 Offset = CurDAG->getTargetConstant(0, ValTy);
261 return true; 261 return true;
262 } 262 }
263 263 return false;
264 // on PIC code Load GA 264 }
265 if (Addr.getOpcode() == MipsISD::Wrapper) { 265
266 Base = Addr.getOperand(0); 266 /// Match frameindex+offset and frameindex|offset
267 Offset = Addr.getOperand(1); 267 bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base,
268 return true; 268 SDValue &Offset,
269 } 269 unsigned OffsetBits) const {
270
271 if (TM.getRelocationModel() != Reloc::PIC_) {
272 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
273 Addr.getOpcode() == ISD::TargetGlobalAddress))
274 return false;
275 }
276
277 // Addresses of the form FI+const or FI|const
278 if (CurDAG->isBaseWithConstantOffset(Addr)) { 270 if (CurDAG->isBaseWithConstantOffset(Addr)) {
279 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)); 271 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
280 if (isInt<16>(CN->getSExtValue())) { 272 if (isIntN(OffsetBits, CN->getSExtValue())) {
273 EVT ValTy = Addr.getValueType();
281 274
282 // If the first operand is a FI, get the TargetFI Node 275 // If the first operand is a FI, get the TargetFI Node
283 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode> 276 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
284 (Addr.getOperand(0))) 277 (Addr.getOperand(0)))
285 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); 278 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
288 281
289 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy); 282 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
290 return true; 283 return true;
291 } 284 }
292 } 285 }
286 return false;
287 }
288
289 /// ComplexPattern used on MipsInstrInfo
290 /// Used on Mips Load/Store instructions
291 bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
292 SDValue &Offset) const {
293 // if Address is FI, get the TargetFrameIndex.
294 if (selectAddrFrameIndex(Addr, Base, Offset))
295 return true;
296
297 // on PIC code Load GA
298 if (Addr.getOpcode() == MipsISD::Wrapper) {
299 Base = Addr.getOperand(0);
300 Offset = Addr.getOperand(1);
301 return true;
302 }
303
304 if (TM.getRelocationModel() != Reloc::PIC_) {
305 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
306 Addr.getOpcode() == ISD::TargetGlobalAddress))
307 return false;
308 }
309
310 // Addresses of the form FI+const or FI|const
311 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
312 return true;
293 313
294 // Operand is a result from an ADD. 314 // Operand is a result from an ADD.
295 if (Addr.getOpcode() == ISD::ADD) { 315 if (Addr.getOpcode() == ISD::ADD) {
296 // When loading from constant pools, load the lower address part in 316 // When loading from constant pools, load the lower address part in
297 // the instruction itself. Example, instead of: 317 // the instruction itself. Example, instead of:
341 SDValue &Offset) const { 361 SDValue &Offset) const {
342 return selectAddrRegImm(Addr, Base, Offset) || 362 return selectAddrRegImm(Addr, Base, Offset) ||
343 selectAddrDefault(Addr, Base, Offset); 363 selectAddrDefault(Addr, Base, Offset);
344 } 364 }
345 365
366 bool MipsSEDAGToDAGISel::selectAddrRegImm10(SDValue Addr, SDValue &Base,
367 SDValue &Offset) const {
368 if (selectAddrFrameIndex(Addr, Base, Offset))
369 return true;
370
371 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
372 return true;
373
374 return false;
375 }
376
346 /// Used on microMIPS Load/Store unaligned instructions (12-bit offset) 377 /// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
347 bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base, 378 bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
348 SDValue &Offset) const { 379 SDValue &Offset) const {
349 EVT ValTy = Addr.getValueType(); 380 if (selectAddrFrameIndex(Addr, Base, Offset))
350 381 return true;
351 // Addresses of the form FI+const or FI|const 382
352 if (CurDAG->isBaseWithConstantOffset(Addr)) { 383 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12))
353 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)); 384 return true;
354 if (isInt<12>(CN->getSExtValue())) {
355
356 // If the first operand is a FI then get the TargetFI Node
357 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
358 (Addr.getOperand(0)))
359 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
360 else
361 Base = Addr.getOperand(0);
362
363 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
364 return true;
365 }
366 }
367 385
368 return false; 386 return false;
369 } 387 }
370 388
371 bool MipsSEDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base, 389 bool MipsSEDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base,
372 SDValue &Offset) const { 390 SDValue &Offset) const {
373 return selectAddrRegImm12(Addr, Base, Offset) || 391 return selectAddrRegImm12(Addr, Base, Offset) ||
374 selectAddrDefault(Addr, Base, Offset); 392 selectAddrDefault(Addr, Base, Offset);
375 } 393 }
376 394
395 bool MipsSEDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base,
396 SDValue &Offset) const {
397 if (selectAddrRegImm10(Addr, Base, Offset))
398 return true;
399
400 if (selectAddrDefault(Addr, Base, Offset))
401 return true;
402
403 return false;
404 }
405
377 // Select constant vector splats. 406 // Select constant vector splats.
378 // 407 //
379 // Returns true and sets Imm if: 408 // Returns true and sets Imm if:
380 // * MSA is enabled 409 // * MSA is enabled
381 // * N is a ISD::BUILD_VECTOR representing a constant splat 410 // * N is a ISD::BUILD_VECTOR representing a constant splat
382 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const { 411 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const {
383 if (!Subtarget.hasMSA()) 412 if (!Subtarget->hasMSA())
384 return false; 413 return false;
385 414
386 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N); 415 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N);
387 416
388 if (Node == NULL) 417 if (!Node)
389 return false; 418 return false;
390 419
391 APInt SplatValue, SplatUndef; 420 APInt SplatValue, SplatUndef;
392 unsigned SplatBitSize; 421 unsigned SplatBitSize;
393 bool HasAnyUndefs; 422 bool HasAnyUndefs;
394 423
395 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, 424 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
396 HasAnyUndefs, 8, 425 HasAnyUndefs, 8,
397 !Subtarget.isLittle())) 426 !Subtarget->isLittle()))
398 return false; 427 return false;
399 428
400 Imm = SplatValue; 429 Imm = SplatValue;
401 430
402 return true; 431 return true;
618 Result = selectAddESubE(Mips::SUBu, InFlag, InFlag.getOperand(0), DL, Node); 647 Result = selectAddESubE(Mips::SUBu, InFlag, InFlag.getOperand(0), DL, Node);
619 return std::make_pair(true, Result); 648 return std::make_pair(true, Result);
620 } 649 }
621 650
622 case ISD::ADDE: { 651 case ISD::ADDE: {
623 if (Subtarget.hasDSP()) // Select DSP instructions, ADDSC and ADDWC. 652 if (Subtarget->hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
624 break; 653 break;
625 SDValue InFlag = Node->getOperand(2); 654 SDValue InFlag = Node->getOperand(2);
626 Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node); 655 Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node);
627 return std::make_pair(true, Result); 656 return std::make_pair(true, Result);
628 } 657 }
629 658
630 case ISD::ConstantFP: { 659 case ISD::ConstantFP: {
631 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node); 660 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
632 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) { 661 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
633 if (Subtarget.hasMips64()) { 662 if (Subtarget->isGP64bit()) {
634 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, 663 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
635 Mips::ZERO_64, MVT::i64); 664 Mips::ZERO_64, MVT::i64);
636 Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero); 665 Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);
637 } else if (Subtarget.isFP64bit()) { 666 } else if (Subtarget->isFP64bit()) {
638 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, 667 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
639 Mips::ZERO, MVT::i32); 668 Mips::ZERO, MVT::i32);
640 Result = CurDAG->getMachineNode(Mips::BuildPairF64_64, DL, MVT::f64, 669 Result = CurDAG->getMachineNode(Mips::BuildPairF64_64, DL, MVT::f64,
641 Zero, Zero); 670 Zero, Zero);
642 } else { 671 } else {
783 bool HasAnyUndefs; 812 bool HasAnyUndefs;
784 unsigned LdiOp; 813 unsigned LdiOp;
785 EVT ResVecTy = BVN->getValueType(0); 814 EVT ResVecTy = BVN->getValueType(0);
786 EVT ViaVecTy; 815 EVT ViaVecTy;
787 816
788 if (!Subtarget.hasMSA() || !BVN->getValueType(0).is128BitVector()) 817 if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector())
789 return std::make_pair(false, (SDNode*)NULL); 818 return std::make_pair(false, nullptr);
790 819
791 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, 820 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
792 HasAnyUndefs, 8, 821 HasAnyUndefs, 8,
793 !Subtarget.isLittle())) 822 !Subtarget->isLittle()))
794 return std::make_pair(false, (SDNode*)NULL); 823 return std::make_pair(false, nullptr);
795 824
796 switch (SplatBitSize) { 825 switch (SplatBitSize) {
797 default: 826 default:
798 return std::make_pair(false, (SDNode*)NULL); 827 return std::make_pair(false, nullptr);
799 case 8: 828 case 8:
800 LdiOp = Mips::LDI_B; 829 LdiOp = Mips::LDI_B;
801 ViaVecTy = MVT::v16i8; 830 ViaVecTy = MVT::v16i8;
802 break; 831 break;
803 case 16: 832 case 16:
813 ViaVecTy = MVT::v2i64; 842 ViaVecTy = MVT::v2i64;
814 break; 843 break;
815 } 844 }
816 845
817 if (!SplatValue.isSignedIntN(10)) 846 if (!SplatValue.isSignedIntN(10))
818 return std::make_pair(false, (SDNode*)NULL); 847 return std::make_pair(false, nullptr);
819 848
820 SDValue Imm = CurDAG->getTargetConstant(SplatValue, 849 SDValue Imm = CurDAG->getTargetConstant(SplatValue,
821 ViaVecTy.getVectorElementType()); 850 ViaVecTy.getVectorElementType());
822 851
823 SDNode *Res = CurDAG->getMachineNode(LdiOp, SDLoc(Node), ViaVecTy, Imm); 852 SDNode *Res = CurDAG->getMachineNode(LdiOp, SDLoc(Node), ViaVecTy, Imm);
839 return std::make_pair(true, Res); 868 return std::make_pair(true, Res);
840 } 869 }
841 870
842 } 871 }
843 872
844 return std::make_pair(false, (SDNode*)NULL); 873 return std::make_pair(false, nullptr);
845 } 874 }
846 875
847 FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) { 876 FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) {
848 return new MipsSEDAGToDAGISel(TM); 877 return new MipsSEDAGToDAGISel(TM);
849 } 878 }