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comparison lib/Target/Sparc/SparcInstrInfo.cpp @ 77:54457678186b LLVM3.6

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LLVM 3.6
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Mon, 08 Sep 2014 22:06:00 +0900
parents 95c75e76d11b
children afa8332a0e37
comparison
equal deleted inserted replaced
34:e874dbf0ad9d 77:54457678186b
22 #include "llvm/CodeGen/MachineMemOperand.h" 22 #include "llvm/CodeGen/MachineMemOperand.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h" 23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/TargetRegistry.h" 25 #include "llvm/Support/TargetRegistry.h"
26 26
27 using namespace llvm;
28
27 #define GET_INSTRINFO_CTOR_DTOR 29 #define GET_INSTRINFO_CTOR_DTOR
28 #include "SparcGenInstrInfo.inc" 30 #include "SparcGenInstrInfo.inc"
29
30 using namespace llvm;
31
32 31
33 // Pin the vtable to this file. 32 // Pin the vtable to this file.
34 void SparcInstrInfo::anchor() {} 33 void SparcInstrInfo::anchor() {}
35 34
36 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST) 35 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
87 86
88 87
89 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC) 88 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
90 { 89 {
91 switch(CC) { 90 switch(CC) {
91 case SPCC::ICC_A: return SPCC::ICC_N;
92 case SPCC::ICC_N: return SPCC::ICC_A;
92 case SPCC::ICC_NE: return SPCC::ICC_E; 93 case SPCC::ICC_NE: return SPCC::ICC_E;
93 case SPCC::ICC_E: return SPCC::ICC_NE; 94 case SPCC::ICC_E: return SPCC::ICC_NE;
94 case SPCC::ICC_G: return SPCC::ICC_LE; 95 case SPCC::ICC_G: return SPCC::ICC_LE;
95 case SPCC::ICC_LE: return SPCC::ICC_G; 96 case SPCC::ICC_LE: return SPCC::ICC_G;
96 case SPCC::ICC_GE: return SPCC::ICC_L; 97 case SPCC::ICC_GE: return SPCC::ICC_L;
102 case SPCC::ICC_POS: return SPCC::ICC_NEG; 103 case SPCC::ICC_POS: return SPCC::ICC_NEG;
103 case SPCC::ICC_NEG: return SPCC::ICC_POS; 104 case SPCC::ICC_NEG: return SPCC::ICC_POS;
104 case SPCC::ICC_VC: return SPCC::ICC_VS; 105 case SPCC::ICC_VC: return SPCC::ICC_VS;
105 case SPCC::ICC_VS: return SPCC::ICC_VC; 106 case SPCC::ICC_VS: return SPCC::ICC_VC;
106 107
108 case SPCC::FCC_A: return SPCC::FCC_N;
109 case SPCC::FCC_N: return SPCC::FCC_A;
107 case SPCC::FCC_U: return SPCC::FCC_O; 110 case SPCC::FCC_U: return SPCC::FCC_O;
108 case SPCC::FCC_O: return SPCC::FCC_U; 111 case SPCC::FCC_O: return SPCC::FCC_U;
109 case SPCC::FCC_G: return SPCC::FCC_ULE; 112 case SPCC::FCC_G: return SPCC::FCC_ULE;
110 case SPCC::FCC_LE: return SPCC::FCC_UG; 113 case SPCC::FCC_LE: return SPCC::FCC_UG;
111 case SPCC::FCC_UG: return SPCC::FCC_LE; 114 case SPCC::FCC_UG: return SPCC::FCC_LE;
152 if (!AllowModify) { 155 if (!AllowModify) {
153 TBB = I->getOperand(0).getMBB(); 156 TBB = I->getOperand(0).getMBB();
154 continue; 157 continue;
155 } 158 }
156 159
157 while (llvm::next(I) != MBB.end()) 160 while (std::next(I) != MBB.end())
158 llvm::next(I)->eraseFromParent(); 161 std::next(I)->eraseFromParent();
159 162
160 Cond.clear(); 163 Cond.clear();
161 FBB = 0; 164 FBB = nullptr;
162 165
163 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 166 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
164 TBB = 0; 167 TBB = nullptr;
165 I->eraseFromParent(); 168 I->eraseFromParent();
166 I = MBB.end(); 169 I = MBB.end();
167 UnCondBrIter = MBB.end(); 170 UnCondBrIter = MBB.end();
168 continue; 171 continue;
169 } 172 }
279 MachineBasicBlock::iterator I, DebugLoc DL, 282 MachineBasicBlock::iterator I, DebugLoc DL,
280 unsigned DestReg, unsigned SrcReg, 283 unsigned DestReg, unsigned SrcReg,
281 bool KillSrc) const { 284 bool KillSrc) const {
282 unsigned numSubRegs = 0; 285 unsigned numSubRegs = 0;
283 unsigned movOpc = 0; 286 unsigned movOpc = 0;
284 const unsigned *subRegIdx = 0; 287 const unsigned *subRegIdx = nullptr;
285 288
286 const unsigned DFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd }; 289 const unsigned DFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd };
287 const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 }; 290 const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 };
288 const unsigned QFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd, 291 const unsigned QFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd,
289 SP::sub_odd64_then_sub_even, 292 SP::sub_odd64_then_sub_even,
323 movOpc = SP::FMOVS; 326 movOpc = SP::FMOVS;
324 } 327 }
325 } else 328 } else
326 llvm_unreachable("Impossible reg-to-reg copy"); 329 llvm_unreachable("Impossible reg-to-reg copy");
327 330
328 if (numSubRegs == 0 || subRegIdx == 0 || movOpc == 0) 331 if (numSubRegs == 0 || subRegIdx == nullptr || movOpc == 0)
329 return; 332 return;
330 333
331 const TargetRegisterInfo *TRI = &getRegisterInfo(); 334 const TargetRegisterInfo *TRI = &getRegisterInfo();
332 MachineInstr *MovMI = 0; 335 MachineInstr *MovMI = nullptr;
333 336
334 for (unsigned i = 0; i != numSubRegs; ++i) { 337 for (unsigned i = 0; i != numSubRegs; ++i) {
335 unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]); 338 unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]);
336 unsigned Src = TRI->getSubReg(SrcReg, subRegIdx[i]); 339 unsigned Src = TRI->getSubReg(SrcReg, subRegIdx[i]);
337 assert(Dst && Src && "Bad sub-register"); 340 assert(Dst && Src && "Bad sub-register");
429 // Insert the set of GlobalBaseReg into the first MBB of the function 432 // Insert the set of GlobalBaseReg into the first MBB of the function
430 MachineBasicBlock &FirstMBB = MF->front(); 433 MachineBasicBlock &FirstMBB = MF->front();
431 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 434 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
432 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 435 MachineRegisterInfo &RegInfo = MF->getRegInfo();
433 436
434 GlobalBaseReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 437 const TargetRegisterClass *PtrRC =
435 438 Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
439 GlobalBaseReg = RegInfo.createVirtualRegister(PtrRC);
436 440
437 DebugLoc dl; 441 DebugLoc dl;
438 442
439 BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg); 443 BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
440 SparcFI->setGlobalBaseReg(GlobalBaseReg); 444 SparcFI->setGlobalBaseReg(GlobalBaseReg);