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comparison test/CodeGen/AArch64/arm64-atomic.ll @ 77:54457678186b LLVM3.6

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LLVM 3.6
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Mon, 08 Sep 2014 22:06:00 +0900
parents
children 60c9769439b8
comparison
equal deleted inserted replaced
34:e874dbf0ad9d 77:54457678186b
1 ; RUN: llc < %s -march=arm64 -verify-machineinstrs -mcpu=cyclone | FileCheck %s
2
3 define i32 @val_compare_and_swap(i32* %p) {
4 ; CHECK-LABEL: val_compare_and_swap:
5 ; CHECK: orr [[NEWVAL_REG:w[0-9]+]], wzr, #0x4
6 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
7 ; CHECK: ldaxr [[RESULT:w[0-9]+]], [x0]
8 ; CHECK: cmp [[RESULT]], #7
9 ; CHECK: b.ne [[LABEL2:.?LBB[0-9]+_[0-9]+]]
10 ; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], [[NEWVAL_REG]], [x0]
11 ; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
12 ; CHECK: [[LABEL2]]:
13 %pair = cmpxchg i32* %p, i32 7, i32 4 acquire acquire
14 %val = extractvalue { i32, i1 } %pair, 0
15 ret i32 %val
16 }
17
18 define i64 @val_compare_and_swap_64(i64* %p) {
19 ; CHECK-LABEL: val_compare_and_swap_64:
20 ; CHECK: orr w[[NEWVAL_REG:[0-9]+]], wzr, #0x4
21 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
22 ; CHECK: ldxr [[RESULT:x[0-9]+]], [x0]
23 ; CHECK: cmp [[RESULT]], #7
24 ; CHECK: b.ne [[LABEL2:.?LBB[0-9]+_[0-9]+]]
25 ; CHECK-NOT: stxr x[[NEWVAL_REG]], x[[NEWVAL_REG]]
26 ; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], x[[NEWVAL_REG]], [x0]
27 ; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
28 ; CHECK: [[LABEL2]]:
29 %pair = cmpxchg i64* %p, i64 7, i64 4 monotonic monotonic
30 %val = extractvalue { i64, i1 } %pair, 0
31 ret i64 %val
32 }
33
34 define i32 @fetch_and_nand(i32* %p) {
35 ; CHECK-LABEL: fetch_and_nand:
36 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
37 ; CHECK: ldxr w[[DEST_REG:[0-9]+]], [x0]
38 ; CHECK: mvn [[TMP_REG:w[0-9]+]], w[[DEST_REG]]
39 ; CHECK: orr [[SCRATCH2_REG:w[0-9]+]], [[TMP_REG]], #0xfffffff8
40 ; CHECK-NOT: stlxr [[SCRATCH2_REG]], [[SCRATCH2_REG]]
41 ; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
42 ; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
43 ; CHECK: mov x0, x[[DEST_REG]]
44 %val = atomicrmw nand i32* %p, i32 7 release
45 ret i32 %val
46 }
47
48 define i64 @fetch_and_nand_64(i64* %p) {
49 ; CHECK-LABEL: fetch_and_nand_64:
50 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
51 ; CHECK: ldaxr x[[DEST_REG:[0-9]+]], [x0]
52 ; CHECK: mvn w[[TMP_REG:[0-9]+]], w[[DEST_REG]]
53 ; CHECK: orr [[SCRATCH2_REG:x[0-9]+]], x[[TMP_REG]], #0xfffffffffffffff8
54 ; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
55 ; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
56 ; CHECK: mov x0, x[[DEST_REG]]
57
58 %val = atomicrmw nand i64* %p, i64 7 acq_rel
59 ret i64 %val
60 }
61
62 define i32 @fetch_and_or(i32* %p) {
63 ; CHECK-LABEL: fetch_and_or:
64 ; CHECK: movz [[OLDVAL_REG:w[0-9]+]], #0x5
65 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
66 ; CHECK: ldaxr w[[DEST_REG:[0-9]+]], [x0]
67 ; CHECK: orr [[SCRATCH2_REG:w[0-9]+]], w[[DEST_REG]], [[OLDVAL_REG]]
68 ; CHECK-NOT: stlxr [[SCRATCH2_REG]], [[SCRATCH2_REG]]
69 ; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
70 ; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
71 ; CHECK: mov x0, x[[DEST_REG]]
72 %val = atomicrmw or i32* %p, i32 5 seq_cst
73 ret i32 %val
74 }
75
76 define i64 @fetch_and_or_64(i64* %p) {
77 ; CHECK: fetch_and_or_64:
78 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
79 ; CHECK: ldxr [[DEST_REG:x[0-9]+]], [x0]
80 ; CHECK: orr [[SCRATCH2_REG:x[0-9]+]], [[DEST_REG]], #0x7
81 ; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
82 ; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
83 ; CHECK: mov x0, [[DEST_REG]]
84 %val = atomicrmw or i64* %p, i64 7 monotonic
85 ret i64 %val
86 }
87
88 define void @acquire_fence() {
89 fence acquire
90 ret void
91 ; CHECK-LABEL: acquire_fence:
92 ; CHECK: dmb ishld
93 }
94
95 define void @release_fence() {
96 fence release
97 ret void
98 ; CHECK-LABEL: release_fence:
99 ; CHECK: dmb ish{{$}}
100 }
101
102 define void @seq_cst_fence() {
103 fence seq_cst
104 ret void
105 ; CHECK-LABEL: seq_cst_fence:
106 ; CHECK: dmb ish{{$}}
107 }
108
109 define i32 @atomic_load(i32* %p) {
110 %r = load atomic i32* %p seq_cst, align 4
111 ret i32 %r
112 ; CHECK-LABEL: atomic_load:
113 ; CHECK: ldar
114 }
115
116 define i8 @atomic_load_relaxed_8(i8* %p, i32 %off32) {
117 ; CHECK-LABEL: atomic_load_relaxed_8:
118 %ptr_unsigned = getelementptr i8* %p, i32 4095
119 %val_unsigned = load atomic i8* %ptr_unsigned monotonic, align 1
120 ; CHECK: ldrb {{w[0-9]+}}, [x0, #4095]
121
122 %ptr_regoff = getelementptr i8* %p, i32 %off32
123 %val_regoff = load atomic i8* %ptr_regoff unordered, align 1
124 %tot1 = add i8 %val_unsigned, %val_regoff
125 ; CHECK: ldrb {{w[0-9]+}}, [x0, w1, sxtw]
126
127 %ptr_unscaled = getelementptr i8* %p, i32 -256
128 %val_unscaled = load atomic i8* %ptr_unscaled monotonic, align 1
129 %tot2 = add i8 %tot1, %val_unscaled
130 ; CHECK: ldurb {{w[0-9]+}}, [x0, #-256]
131
132 %ptr_random = getelementptr i8* %p, i32 1191936 ; 0x123000 (i.e. ADD imm)
133 %val_random = load atomic i8* %ptr_random unordered, align 1
134 %tot3 = add i8 %tot2, %val_random
135 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
136 ; CHECK: ldrb {{w[0-9]+}}, [x[[ADDR]]]
137
138 ret i8 %tot3
139 }
140
141 define i16 @atomic_load_relaxed_16(i16* %p, i32 %off32) {
142 ; CHECK-LABEL: atomic_load_relaxed_16:
143 %ptr_unsigned = getelementptr i16* %p, i32 4095
144 %val_unsigned = load atomic i16* %ptr_unsigned monotonic, align 2
145 ; CHECK: ldrh {{w[0-9]+}}, [x0, #8190]
146
147 %ptr_regoff = getelementptr i16* %p, i32 %off32
148 %val_regoff = load atomic i16* %ptr_regoff unordered, align 2
149 %tot1 = add i16 %val_unsigned, %val_regoff
150 ; CHECK: ldrh {{w[0-9]+}}, [x0, w1, sxtw #1]
151
152 %ptr_unscaled = getelementptr i16* %p, i32 -128
153 %val_unscaled = load atomic i16* %ptr_unscaled monotonic, align 2
154 %tot2 = add i16 %tot1, %val_unscaled
155 ; CHECK: ldurh {{w[0-9]+}}, [x0, #-256]
156
157 %ptr_random = getelementptr i16* %p, i32 595968 ; 0x123000/2 (i.e. ADD imm)
158 %val_random = load atomic i16* %ptr_random unordered, align 2
159 %tot3 = add i16 %tot2, %val_random
160 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
161 ; CHECK: ldrh {{w[0-9]+}}, [x[[ADDR]]]
162
163 ret i16 %tot3
164 }
165
166 define i32 @atomic_load_relaxed_32(i32* %p, i32 %off32) {
167 ; CHECK-LABEL: atomic_load_relaxed_32:
168 %ptr_unsigned = getelementptr i32* %p, i32 4095
169 %val_unsigned = load atomic i32* %ptr_unsigned monotonic, align 4
170 ; CHECK: ldr {{w[0-9]+}}, [x0, #16380]
171
172 %ptr_regoff = getelementptr i32* %p, i32 %off32
173 %val_regoff = load atomic i32* %ptr_regoff unordered, align 4
174 %tot1 = add i32 %val_unsigned, %val_regoff
175 ; CHECK: ldr {{w[0-9]+}}, [x0, w1, sxtw #2]
176
177 %ptr_unscaled = getelementptr i32* %p, i32 -64
178 %val_unscaled = load atomic i32* %ptr_unscaled monotonic, align 4
179 %tot2 = add i32 %tot1, %val_unscaled
180 ; CHECK: ldur {{w[0-9]+}}, [x0, #-256]
181
182 %ptr_random = getelementptr i32* %p, i32 297984 ; 0x123000/4 (i.e. ADD imm)
183 %val_random = load atomic i32* %ptr_random unordered, align 4
184 %tot3 = add i32 %tot2, %val_random
185 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
186 ; CHECK: ldr {{w[0-9]+}}, [x[[ADDR]]]
187
188 ret i32 %tot3
189 }
190
191 define i64 @atomic_load_relaxed_64(i64* %p, i32 %off32) {
192 ; CHECK-LABEL: atomic_load_relaxed_64:
193 %ptr_unsigned = getelementptr i64* %p, i32 4095
194 %val_unsigned = load atomic i64* %ptr_unsigned monotonic, align 8
195 ; CHECK: ldr {{x[0-9]+}}, [x0, #32760]
196
197 %ptr_regoff = getelementptr i64* %p, i32 %off32
198 %val_regoff = load atomic i64* %ptr_regoff unordered, align 8
199 %tot1 = add i64 %val_unsigned, %val_regoff
200 ; CHECK: ldr {{x[0-9]+}}, [x0, w1, sxtw #3]
201
202 %ptr_unscaled = getelementptr i64* %p, i32 -32
203 %val_unscaled = load atomic i64* %ptr_unscaled monotonic, align 8
204 %tot2 = add i64 %tot1, %val_unscaled
205 ; CHECK: ldur {{x[0-9]+}}, [x0, #-256]
206
207 %ptr_random = getelementptr i64* %p, i32 148992 ; 0x123000/8 (i.e. ADD imm)
208 %val_random = load atomic i64* %ptr_random unordered, align 8
209 %tot3 = add i64 %tot2, %val_random
210 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
211 ; CHECK: ldr {{x[0-9]+}}, [x[[ADDR]]]
212
213 ret i64 %tot3
214 }
215
216
217 define void @atomc_store(i32* %p) {
218 store atomic i32 4, i32* %p seq_cst, align 4
219 ret void
220 ; CHECK-LABEL: atomc_store:
221 ; CHECK: stlr
222 }
223
224 define void @atomic_store_relaxed_8(i8* %p, i32 %off32, i8 %val) {
225 ; CHECK-LABEL: atomic_store_relaxed_8:
226 %ptr_unsigned = getelementptr i8* %p, i32 4095
227 store atomic i8 %val, i8* %ptr_unsigned monotonic, align 1
228 ; CHECK: strb {{w[0-9]+}}, [x0, #4095]
229
230 %ptr_regoff = getelementptr i8* %p, i32 %off32
231 store atomic i8 %val, i8* %ptr_regoff unordered, align 1
232 ; CHECK: strb {{w[0-9]+}}, [x0, w1, sxtw]
233
234 %ptr_unscaled = getelementptr i8* %p, i32 -256
235 store atomic i8 %val, i8* %ptr_unscaled monotonic, align 1
236 ; CHECK: sturb {{w[0-9]+}}, [x0, #-256]
237
238 %ptr_random = getelementptr i8* %p, i32 1191936 ; 0x123000 (i.e. ADD imm)
239 store atomic i8 %val, i8* %ptr_random unordered, align 1
240 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
241 ; CHECK: strb {{w[0-9]+}}, [x[[ADDR]]]
242
243 ret void
244 }
245
246 define void @atomic_store_relaxed_16(i16* %p, i32 %off32, i16 %val) {
247 ; CHECK-LABEL: atomic_store_relaxed_16:
248 %ptr_unsigned = getelementptr i16* %p, i32 4095
249 store atomic i16 %val, i16* %ptr_unsigned monotonic, align 2
250 ; CHECK: strh {{w[0-9]+}}, [x0, #8190]
251
252 %ptr_regoff = getelementptr i16* %p, i32 %off32
253 store atomic i16 %val, i16* %ptr_regoff unordered, align 2
254 ; CHECK: strh {{w[0-9]+}}, [x0, w1, sxtw #1]
255
256 %ptr_unscaled = getelementptr i16* %p, i32 -128
257 store atomic i16 %val, i16* %ptr_unscaled monotonic, align 2
258 ; CHECK: sturh {{w[0-9]+}}, [x0, #-256]
259
260 %ptr_random = getelementptr i16* %p, i32 595968 ; 0x123000/2 (i.e. ADD imm)
261 store atomic i16 %val, i16* %ptr_random unordered, align 2
262 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
263 ; CHECK: strh {{w[0-9]+}}, [x[[ADDR]]]
264
265 ret void
266 }
267
268 define void @atomic_store_relaxed_32(i32* %p, i32 %off32, i32 %val) {
269 ; CHECK-LABEL: atomic_store_relaxed_32:
270 %ptr_unsigned = getelementptr i32* %p, i32 4095
271 store atomic i32 %val, i32* %ptr_unsigned monotonic, align 4
272 ; CHECK: str {{w[0-9]+}}, [x0, #16380]
273
274 %ptr_regoff = getelementptr i32* %p, i32 %off32
275 store atomic i32 %val, i32* %ptr_regoff unordered, align 4
276 ; CHECK: str {{w[0-9]+}}, [x0, w1, sxtw #2]
277
278 %ptr_unscaled = getelementptr i32* %p, i32 -64
279 store atomic i32 %val, i32* %ptr_unscaled monotonic, align 4
280 ; CHECK: stur {{w[0-9]+}}, [x0, #-256]
281
282 %ptr_random = getelementptr i32* %p, i32 297984 ; 0x123000/4 (i.e. ADD imm)
283 store atomic i32 %val, i32* %ptr_random unordered, align 4
284 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
285 ; CHECK: str {{w[0-9]+}}, [x[[ADDR]]]
286
287 ret void
288 }
289
290 define void @atomic_store_relaxed_64(i64* %p, i32 %off32, i64 %val) {
291 ; CHECK-LABEL: atomic_store_relaxed_64:
292 %ptr_unsigned = getelementptr i64* %p, i32 4095
293 store atomic i64 %val, i64* %ptr_unsigned monotonic, align 8
294 ; CHECK: str {{x[0-9]+}}, [x0, #32760]
295
296 %ptr_regoff = getelementptr i64* %p, i32 %off32
297 store atomic i64 %val, i64* %ptr_regoff unordered, align 8
298 ; CHECK: str {{x[0-9]+}}, [x0, w1, sxtw #3]
299
300 %ptr_unscaled = getelementptr i64* %p, i32 -32
301 store atomic i64 %val, i64* %ptr_unscaled monotonic, align 8
302 ; CHECK: stur {{x[0-9]+}}, [x0, #-256]
303
304 %ptr_random = getelementptr i64* %p, i32 148992 ; 0x123000/8 (i.e. ADD imm)
305 store atomic i64 %val, i64* %ptr_random unordered, align 8
306 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
307 ; CHECK: str {{x[0-9]+}}, [x[[ADDR]]]
308
309 ret void
310 }
311
312 ; rdar://11531169
313 ; rdar://11531308
314
315 %"class.X::Atomic" = type { %struct.x_atomic_t }
316 %struct.x_atomic_t = type { i32 }
317
318 @counter = external hidden global %"class.X::Atomic", align 4
319
320 define i32 @next_id() nounwind optsize ssp align 2 {
321 entry:
322 %0 = atomicrmw add i32* getelementptr inbounds (%"class.X::Atomic"* @counter, i64 0, i32 0, i32 0), i32 1 seq_cst
323 %add.i = add i32 %0, 1
324 %tobool = icmp eq i32 %add.i, 0
325 br i1 %tobool, label %if.else, label %return
326
327 if.else: ; preds = %entry
328 %1 = atomicrmw add i32* getelementptr inbounds (%"class.X::Atomic"* @counter, i64 0, i32 0, i32 0), i32 1 seq_cst
329 %add.i2 = add i32 %1, 1
330 br label %return
331
332 return: ; preds = %if.else, %entry
333 %retval.0 = phi i32 [ %add.i2, %if.else ], [ %add.i, %entry ]
334 ret i32 %retval.0
335 }