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comparison test/CodeGen/AArch64/arm64-elf-globals.ll @ 77:54457678186b LLVM3.6

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LLVM 3.6
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Mon, 08 Sep 2014 22:06:00 +0900
parents
children afa8332a0e37
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34:e874dbf0ad9d 77:54457678186b
1 ; RUN: llc -mtriple=arm64-linux-gnu -o - %s -mcpu=cyclone | FileCheck %s
2 ; RUN: llc -mtriple=arm64-linux-gnu -o - %s -O0 -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST
3 ; RUN: llc -mtriple=arm64-linux-gnu -relocation-model=pic -o - %s -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-PIC
4 ; RUN: llc -mtriple=arm64-linux-gnu -O0 -relocation-model=pic -o - %s -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST-PIC
5
6 @var8 = external global i8, align 1
7 @var16 = external global i16, align 2
8 @var32 = external global i32, align 4
9 @var64 = external global i64, align 8
10
11 define i8 @test_i8(i8 %new) {
12 %val = load i8* @var8, align 1
13 store i8 %new, i8* @var8
14 ret i8 %val
15 ; CHECK-LABEL: test_i8:
16 ; CHECK: adrp x[[HIREG:[0-9]+]], var8
17 ; CHECK: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
18 ; CHECK: strb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
19
20 ; CHECK-PIC-LABEL: test_i8:
21 ; CHECK-PIC: adrp x[[HIREG:[0-9]+]], :got:var8
22 ; CHECK-PIC: ldr x[[VAR_ADDR:[0-9]+]], [x[[HIREG]], :got_lo12:var8]
23 ; CHECK-PIC: ldrb {{w[0-9]+}}, [x[[VAR_ADDR]]]
24
25 ; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var8
26 ; CHECK-FAST: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
27
28 ; CHECK-FAST-PIC: adrp x[[HIREG:[0-9]+]], :got:var8
29 ; CHECK-FAST-PIC: ldr x[[VARADDR:[0-9]+]], [x[[HIREG]], :got_lo12:var8]
30 ; CHECK-FAST-PIC: ldr {{w[0-9]+}}, [x[[VARADDR]]]
31 }
32
33 define i16 @test_i16(i16 %new) {
34 %val = load i16* @var16, align 2
35 store i16 %new, i16* @var16
36 ret i16 %val
37 ; CHECK-LABEL: test_i16:
38 ; CHECK: adrp x[[HIREG:[0-9]+]], var16
39 ; CHECK: ldrh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
40 ; CHECK: strh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
41
42 ; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var16
43 ; CHECK-FAST: ldrh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
44 }
45
46 define i32 @test_i32(i32 %new) {
47 %val = load i32* @var32, align 4
48 store i32 %new, i32* @var32
49 ret i32 %val
50 ; CHECK-LABEL: test_i32:
51 ; CHECK: adrp x[[HIREG:[0-9]+]], var32
52 ; CHECK: ldr {{w[0-9]+}}, [x[[HIREG]], :lo12:var32]
53 ; CHECK: str {{w[0-9]+}}, [x[[HIREG]], :lo12:var32]
54
55 ; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var32
56 ; CHECK-FAST: add {{x[0-9]+}}, x[[HIREG]], :lo12:var32
57 }
58
59 define i64 @test_i64(i64 %new) {
60 %val = load i64* @var64, align 8
61 store i64 %new, i64* @var64
62 ret i64 %val
63 ; CHECK-LABEL: test_i64:
64 ; CHECK: adrp x[[HIREG:[0-9]+]], var64
65 ; CHECK: ldr {{x[0-9]+}}, [x[[HIREG]], :lo12:var64]
66 ; CHECK: str {{x[0-9]+}}, [x[[HIREG]], :lo12:var64]
67
68 ; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var64
69 ; CHECK-FAST: add {{x[0-9]+}}, x[[HIREG]], :lo12:var64
70 }
71
72 define i64* @test_addr() {
73 ret i64* @var64
74 ; CHECK-LABEL: test_addr:
75 ; CHECK: adrp [[HIREG:x[0-9]+]], var64
76 ; CHECK: add x0, [[HIREG]], :lo12:var64
77
78 ; CHECK-FAST: adrp [[HIREG:x[0-9]+]], var64
79 ; CHECK-FAST: add x0, [[HIREG]], :lo12:var64
80 }
81
82 @hiddenvar = hidden global i32 0, align 4
83 @protectedvar = protected global i32 0, align 4
84
85 define i32 @test_vis() {
86 %lhs = load i32* @hiddenvar, align 4
87 %rhs = load i32* @protectedvar, align 4
88 %ret = add i32 %lhs, %rhs
89 ret i32 %ret
90 ; CHECK-PIC: adrp {{x[0-9]+}}, hiddenvar
91 ; CHECK-PIC: ldr {{w[0-9]+}}, [{{x[0-9]+}}, :lo12:hiddenvar]
92 ; CHECK-PIC: adrp {{x[0-9]+}}, protectedvar
93 ; CHECK-PIC: ldr {{w[0-9]+}}, [{{x[0-9]+}}, :lo12:protectedvar]
94 }
95
96 @var_default = external global [2 x i32]
97
98 define i32 @test_default_align() {
99 %addr = getelementptr [2 x i32]* @var_default, i32 0, i32 0
100 %val = load i32* %addr
101 ret i32 %val
102 ; CHECK-LABEL: test_default_align:
103 ; CHECK: adrp x[[HIREG:[0-9]+]], var_default
104 ; CHECK: ldr w0, [x[[HIREG]], :lo12:var_default]
105 }
106
107 define i64 @test_default_unaligned() {
108 %addr = bitcast [2 x i32]* @var_default to i64*
109 %val = load i64* %addr
110 ret i64 %val
111 ; CHECK-LABEL: test_default_unaligned:
112 ; CHECK: adrp [[HIREG:x[0-9]+]], var_default
113 ; CHECK: add x[[ADDR:[0-9]+]], [[HIREG]], :lo12:var_default
114 ; CHECK: ldr x0, [x[[ADDR]]]
115 }