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comparison test/CodeGen/AArch64/arm64-fast-isel-gv.ll @ 77:54457678186b LLVM3.6

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LLVM 3.6
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Mon, 08 Sep 2014 22:06:00 +0900
parents
children afa8332a0e37
comparison
equal deleted inserted replaced
34:e874dbf0ad9d 77:54457678186b
1 ; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
2
3 ; Test load/store of global value from global offset table.
4 @seed = common global i64 0, align 8
5
6 define void @Initrand() nounwind {
7 entry:
8 ; CHECK: @Initrand
9 ; CHECK: adrp [[REG:x[0-9]+]], _seed@GOTPAGE
10 ; CHECK: ldr [[REG2:x[0-9]+]], {{\[}}[[REG]], _seed@GOTPAGEOFF{{\]}}
11 ; CHECK: str {{x[0-9]+}}, {{\[}}[[REG2]]{{\]}}
12 store i64 74755, i64* @seed, align 8
13 ret void
14 }
15
16 define i32 @Rand() nounwind {
17 entry:
18 ; CHECK: @Rand
19 ; CHECK: adrp [[REG1:x[0-9]+]], _seed@GOTPAGE
20 ; CHECK: ldr [[REG2:x[0-9]+]], {{\[}}[[REG1]], _seed@GOTPAGEOFF{{\]}}
21 ; CHECK: movz [[REG3:x[0-9]+]], #0x3619
22 ; CHECK: movz [[REG4:x[0-9]+]], #0x51d
23 ; CHECK: ldr [[REG5:x[0-9]+]], {{\[}}[[REG2]]{{\]}}
24 ; CHECK: mul [[REG6:x[0-9]+]], [[REG5]], [[REG4]]
25 ; CHECK: add [[REG7:x[0-9]+]], [[REG6]], [[REG3]]
26 ; CHECK: and [[REG8:x[0-9]+]], [[REG7]], #0xffff
27 ; CHECK: str [[REG8]], {{\[}}[[REG1]]{{\]}}
28 ; CHECK: ldr {{x[0-9]+}}, {{\[}}[[REG1]]{{\]}}
29 %0 = load i64* @seed, align 8
30 %mul = mul nsw i64 %0, 1309
31 %add = add nsw i64 %mul, 13849
32 %and = and i64 %add, 65535
33 store i64 %and, i64* @seed, align 8
34 %1 = load i64* @seed, align 8
35 %conv = trunc i64 %1 to i32
36 ret i32 %conv
37 }