Mercurial > hg > CbC > CbC_llvm
comparison test/CodeGen/AArch64/arm64-shrink-v1i64.ll @ 77:54457678186b LLVM3.6
LLVM 3.6
| author | Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> |
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| date | Mon, 08 Sep 2014 22:06:00 +0900 |
| parents | |
| children | 1172e4bd9c6f |
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| 34:e874dbf0ad9d | 77:54457678186b |
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| 1 ; RUN: llc -march=arm64 < %s | |
| 2 | |
| 3 ; The DAGCombiner tries to do following shrink: | |
| 4 ; Convert x+y to (VT)((SmallVT)x+(SmallVT)y) | |
| 5 ; But currently it can't handle vector type and will trigger an assertion failure | |
| 6 ; when it tries to generate an add mixed using vector type and scaler type. | |
| 7 ; This test checks that such assertion failur should not happen. | |
| 8 define <1 x i64> @dotest(<1 x i64> %in0) { | |
| 9 entry: | |
| 10 %0 = add <1 x i64> %in0, %in0 | |
| 11 %vshl_n = shl <1 x i64> %0, <i64 32> | |
| 12 %vsra_n = ashr <1 x i64> %vshl_n, <i64 32> | |
| 13 ret <1 x i64> %vsra_n | |
| 14 } |