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comparison test/CodeGen/PowerPC/vsx-spill.ll @ 77:54457678186b LLVM3.6

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LLVM 3.6
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Mon, 08 Sep 2014 22:06:00 +0900
parents
children 60c9769439b8
comparison
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34:e874dbf0ad9d 77:54457678186b
1 ; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck %s
2 target datalayout = "E-m:e-i64:64-n32:64"
3 target triple = "powerpc64-unknown-linux-gnu"
4
5 define double @foo1(double %a) nounwind {
6 entry:
7 call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind
8 br label %return
9
10 ; CHECK: @foo1
11 ; CHECK: xxlor [[R1:[0-9]+]], 1, 1
12 ; CHECK: xxlor 1, [[R1]], [[R1]]
13 ; CHECK: blr
14
15 return: ; preds = %entry
16 ret double %a
17 }
18
19 define double @foo2(double %a) nounwind {
20 entry:
21 %b = fadd double %a, %a
22 call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind
23 br label %return
24
25 ; CHECK: @foo2
26 ; CHECK: {{xxlor|xsadddp}} [[R1:[0-9]+]], 1, 1
27 ; CHECK: {{xxlor|xsadddp}} 1, [[R1]], [[R1]]
28 ; CHECK: blr
29
30 return: ; preds = %entry
31 ret double %b
32 }
33
34 define double @foo3(double %a) nounwind {
35 entry:
36 call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31},~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"() nounwind
37 br label %return
38
39 ; CHECK: @foo3
40 ; CHECK: stxsdx 1,
41 ; CHECK: lxsdx [[R1:[0-9]+]],
42 ; CHECK: xsadddp 1, [[R1]], [[R1]]
43 ; CHECK: blr
44
45 return: ; preds = %entry
46 %b = fadd double %a, %a
47 ret double %b
48 }
49