Mercurial > hg > CbC > CbC_llvm

comparison lib/Target/Mips/MipsInstrFPU.td @ 83:60c9769439b8 LLVM3.7

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LLVM 3.7
author Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
date Wed, 18 Feb 2015 14:55:36 +0900
parents 54457678186b
children afa8332a0e37
comparison
equal deleted inserted replaced
78:af83660cff7b 83:60c9769439b8
209 FrmFI, opstr> { 209 FrmFI, opstr> {
210 let AddedComplexity = 20; 210 let AddedComplexity = 20;
211 } 211 }
212 212
213 class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin, 213 class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
214 SDPatternOperator Op = null_frag> : 214 SDPatternOperator Op = null_frag, bit DelaySlot = 1> :
215 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset), 215 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
216 !strconcat(opstr, "\t$fcc, $offset"), 216 !strconcat(opstr, "\t$fcc, $offset"),
217 [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin, 217 [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin,
218 FrmFI, opstr> { 218 FrmFI, opstr> {
219 let isBranch = 1; 219 let isBranch = 1;
220 let isTerminator = 1; 220 let isTerminator = 1;
221 let hasDelaySlot = 1; 221 let hasDelaySlot = DelaySlot;
222 let Defs = [AT]; 222 let Defs = [AT];
223 } 223 }
224 224
225 class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin, 225 class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
226 SDPatternOperator OpNode = null_frag> : 226 SDPatternOperator OpNode = null_frag> :
402 def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>, 402 def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>,
403 ISA_MIPS2, FGR_32; 403 ISA_MIPS2, FGR_32;
404 def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>, 404 def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>,
405 ISA_MIPS2, FGR_32; 405 ISA_MIPS2, FGR_32;
406 406
407 // Cop2 Memory Instructions
408 // FIXME: These aren't really FPU instructions and as such don't belong in this
409 // file
410 def LWC2 : LW_FT<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
411 ISA_MIPS1_NOT_32R6_64R6;
412 def SWC2 : SW_FT<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
413 ISA_MIPS1_NOT_32R6_64R6;
414 def LDC2 : LW_FT<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
415 ISA_MIPS2_NOT_32R6_64R6;
416 def SDC2 : SW_FT<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
417 ISA_MIPS2_NOT_32R6_64R6;
418
419 // Cop3 Memory Instructions
420 // FIXME: These aren't really FPU instructions and as such don't belong in this
421 // file
422 let DecoderNamespace = "COP3_" in {
423 def LWC3 : LW_FT<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
424 def SWC3 : SW_FT<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
425 def LDC3 : LW_FT<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>,
426 ISA_MIPS2;
427 def SDC3 : SW_FT<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
428 ISA_MIPS2;
429 }
430
431 // Indexed loads and stores. 407 // Indexed loads and stores.
432 // Base register + offset register addressing mode (indicated by "x" in the 408 // Base register + offset register addressing mode (indicated by "x" in the
433 // instruction mnemonic) is disallowed under NaCl. 409 // instruction mnemonic) is disallowed under NaCl.
434 let AdditionalPredicates = [IsNotNaCl] in { 410 let AdditionalPredicates = [IsNotNaCl] in {
435 def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>, 411 def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>,
528 def MIPS_BRANCH_F : PatLeaf<(i32 0)>; 504 def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
529 def MIPS_BRANCH_T : PatLeaf<(i32 1)>; 505 def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
530 506
531 def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, IIBranch, MIPS_BRANCH_F>, 507 def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, IIBranch, MIPS_BRANCH_F>,
532 BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6; 508 BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
509 def BC1FL : MMRel, BC1F_FT<"bc1fl", brtarget, IIBranch, MIPS_BRANCH_F, 0>,
510 BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6;
533 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, IIBranch, MIPS_BRANCH_T>, 511 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, IIBranch, MIPS_BRANCH_T>,
534 BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6; 512 BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;
513 def BC1TL : MMRel, BC1F_FT<"bc1tl", brtarget, IIBranch, MIPS_BRANCH_T, 0>,
514 BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6;
535 515
536 //===----------------------------------------------------------------------===// 516 //===----------------------------------------------------------------------===//
537 // Floating Point Flag Conditions 517 // Floating Point Flag Conditions
538 //===----------------------------------------------------------------------===// 518 //===----------------------------------------------------------------------===//
539 // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h. 519 // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
595 //===----------------------------------------------------------------------===// 575 //===----------------------------------------------------------------------===//
596 // InstAliases. 576 // InstAliases.
597 //===----------------------------------------------------------------------===// 577 //===----------------------------------------------------------------------===//
598 def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>, 578 def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>,
599 ISA_MIPS1_NOT_32R6_64R6; 579 ISA_MIPS1_NOT_32R6_64R6;
580 def : MipsInstAlias<"bc1tl $offset", (BC1TL FCC0, brtarget:$offset)>,
581 ISA_MIPS2_NOT_32R6_64R6;
600 def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>, 582 def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>,
601 ISA_MIPS1_NOT_32R6_64R6; 583 ISA_MIPS1_NOT_32R6_64R6;
584 def : MipsInstAlias<"bc1fl $offset", (BC1FL FCC0, brtarget:$offset)>,
585 ISA_MIPS2_NOT_32R6_64R6;
602 586
603 //===----------------------------------------------------------------------===// 587 //===----------------------------------------------------------------------===//
604 // Floating Point Patterns 588 // Floating Point Patterns
605 //===----------------------------------------------------------------------===// 589 //===----------------------------------------------------------------------===//
606 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>; 590 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;