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comparison lib/Target/Sparc/SparcTargetMachine.cpp @ 83:60c9769439b8 LLVM3.7

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LLVM 3.7
author Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
date Wed, 18 Feb 2015 14:55:36 +0900
parents 54457678186b
children afa8332a0e37
comparison
equal deleted inserted replaced
78:af83660cff7b 83:60c9769439b8
9 // 9 //
10 // 10 //
11 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===//
12 12
13 #include "SparcTargetMachine.h" 13 #include "SparcTargetMachine.h"
14 #include "SparcTargetObjectFile.h"
14 #include "Sparc.h" 15 #include "Sparc.h"
15 #include "llvm/CodeGen/Passes.h" 16 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/PassManager.h" 17 #include "llvm/IR/LegacyPassManager.h"
17 #include "llvm/Support/TargetRegistry.h" 18 #include "llvm/Support/TargetRegistry.h"
18 using namespace llvm; 19 using namespace llvm;
19 20
20 extern "C" void LLVMInitializeSparcTarget() { 21 extern "C" void LLVMInitializeSparcTarget() {
21 // Register the target. 22 // Register the target.
22 RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget); 23 RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget);
23 RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target); 24 RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target);
25 }
26
27 static std::string computeDataLayout(bool is64Bit) {
28 // Sparc is big endian.
29 std::string Ret = "E-m:e";
30
31 // Some ABIs have 32bit pointers.
32 if (!is64Bit)
33 Ret += "-p:32:32";
34
35 // Alignments for 64 bit integers.
36 Ret += "-i64:64";
37
38 // On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
39 // On SparcV9 registers can hold 64 or 32 bits, on others only 32.
40 if (is64Bit)
41 Ret += "-n32:64";
42 else
43 Ret += "-f128:64-n32";
44
45 if (is64Bit)
46 Ret += "-S128";
47 else
48 Ret += "-S64";
49
50 return Ret;
24 } 51 }
25 52
26 /// SparcTargetMachine ctor - Create an ILP32 architecture model 53 /// SparcTargetMachine ctor - Create an ILP32 architecture model
27 /// 54 ///
28 SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, 55 SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
30 const TargetOptions &Options, 57 const TargetOptions &Options,
31 Reloc::Model RM, CodeModel::Model CM, 58 Reloc::Model RM, CodeModel::Model CM,
32 CodeGenOpt::Level OL, 59 CodeGenOpt::Level OL,
33 bool is64bit) 60 bool is64bit)
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 61 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
62 TLOF(make_unique<SparcELFTargetObjectFile>()),
63 DL(computeDataLayout(is64bit)),
35 Subtarget(TT, CPU, FS, *this, is64bit) { 64 Subtarget(TT, CPU, FS, *this, is64bit) {
36 initAsmInfo(); 65 initAsmInfo();
37 } 66 }
67
68 SparcTargetMachine::~SparcTargetMachine() {}
38 69
39 namespace { 70 namespace {
40 /// Sparc Code Generator Pass Configuration Options. 71 /// Sparc Code Generator Pass Configuration Options.
41 class SparcPassConfig : public TargetPassConfig { 72 class SparcPassConfig : public TargetPassConfig {
42 public: 73 public:
45 76
46 SparcTargetMachine &getSparcTargetMachine() const { 77 SparcTargetMachine &getSparcTargetMachine() const {
47 return getTM<SparcTargetMachine>(); 78 return getTM<SparcTargetMachine>();
48 } 79 }
49 80
81 void addIRPasses() override;
50 bool addInstSelector() override; 82 bool addInstSelector() override;
51 bool addPreEmitPass() override; 83 void addPreEmitPass() override;
52 }; 84 };
53 } // namespace 85 } // namespace
54 86
55 TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) { 87 TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
56 return new SparcPassConfig(this, PM); 88 return new SparcPassConfig(this, PM);
57 } 89 }
58 90
91 void SparcPassConfig::addIRPasses() {
92 addPass(createAtomicExpandPass(&getSparcTargetMachine()));
93
94 TargetPassConfig::addIRPasses();
95 }
96
59 bool SparcPassConfig::addInstSelector() { 97 bool SparcPassConfig::addInstSelector() {
60 addPass(createSparcISelDag(getSparcTargetMachine())); 98 addPass(createSparcISelDag(getSparcTargetMachine()));
61 return false; 99 return false;
62 } 100 }
63 101
64 /// addPreEmitPass - This pass may be implemented by targets that want to run 102 void SparcPassConfig::addPreEmitPass(){
65 /// passes immediately before machine code is emitted. This should return
66 /// true if -print-machineinstrs should print out the code after the passes.
67 bool SparcPassConfig::addPreEmitPass(){
68 addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine())); 103 addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
69 return true;
70 } 104 }
71 105
72 void SparcV8TargetMachine::anchor() { } 106 void SparcV8TargetMachine::anchor() { }
73 107
74 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, 108 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T,