Mercurial > hg > CbC > CbC_llvm
comparison test/CodeGen/PowerPC/fast-isel-ret.ll @ 83:60c9769439b8 LLVM3.7
LLVM 3.7
author | Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp> |
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date | Wed, 18 Feb 2015 14:55:36 +0900 |
parents | 95c75e76d11b |
children | afa8332a0e37 |
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78:af83660cff7b | 83:60c9769439b8 |
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1 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 | 1 ; FIXME: FastISel currently returns false if it hits code that uses VSX |
2 ; registers and with -fast-isel-abort turned on the test case will then fail. | |
3 ; When fastisel better supports VSX fix up this test case. | |
4 ; | |
5 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64 | |
6 | |
7 define zeroext i1 @rettrue() nounwind uwtable ssp { | |
8 entry: | |
9 ; ELF64-LABEL: rettrue | |
10 ; ELF64: li 3, 1 | |
11 ; ELF64: blr | |
12 ret i1 true | |
13 } | |
14 | |
15 define zeroext i1 @retfalse() nounwind uwtable ssp { | |
16 entry: | |
17 ; ELF64-LABEL: retfalse | |
18 ; ELF64: li 3, 0 | |
19 ; ELF64: blr | |
20 ret i1 false | |
21 } | |
22 | |
23 define signext i1 @retstrue() nounwind uwtable ssp { | |
24 entry: | |
25 ; ELF64-LABEL: retstrue | |
26 ; ELF64: li 3, -1 | |
27 ; ELF64: blr | |
28 ret i1 true | |
29 } | |
30 | |
31 define signext i1 @retsfalse() nounwind uwtable ssp { | |
32 entry: | |
33 ; ELF64-LABEL: retsfalse | |
34 ; ELF64: li 3, 0 | |
35 ; ELF64: blr | |
36 ret i1 false | |
37 } | |
2 | 38 |
3 define signext i8 @ret2(i8 signext %a) nounwind uwtable ssp { | 39 define signext i8 @ret2(i8 signext %a) nounwind uwtable ssp { |
4 entry: | 40 entry: |
5 ; ELF64: ret2 | 41 ; ELF64-LABEL: ret2 |
6 ; ELF64: extsb | 42 ; ELF64: extsb |
7 ; ELF64: blr | 43 ; ELF64: blr |
8 ret i8 %a | 44 ret i8 %a |
9 } | 45 } |
10 | 46 |
11 define zeroext i8 @ret3(i8 signext %a) nounwind uwtable ssp { | 47 define zeroext i8 @ret3(i8 signext %a) nounwind uwtable ssp { |
12 entry: | 48 entry: |
13 ; ELF64: ret3 | 49 ; ELF64-LABEL: ret3 |
14 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 | 50 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 |
15 ; ELF64: blr | 51 ; ELF64: blr |
16 ret i8 %a | 52 ret i8 %a |
17 } | 53 } |
18 | 54 |
19 define signext i16 @ret4(i16 signext %a) nounwind uwtable ssp { | 55 define signext i16 @ret4(i16 signext %a) nounwind uwtable ssp { |
20 entry: | 56 entry: |
21 ; ELF64: ret4 | 57 ; ELF64-LABEL: ret4 |
22 ; ELF64: extsh | 58 ; ELF64: extsh |
23 ; ELF64: blr | 59 ; ELF64: blr |
24 ret i16 %a | 60 ret i16 %a |
25 } | 61 } |
26 | 62 |
27 define zeroext i16 @ret5(i16 signext %a) nounwind uwtable ssp { | 63 define zeroext i16 @ret5(i16 signext %a) nounwind uwtable ssp { |
28 entry: | 64 entry: |
29 ; ELF64: ret5 | 65 ; ELF64-LABEL: ret5 |
30 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 | 66 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 |
31 ; ELF64: blr | 67 ; ELF64: blr |
32 ret i16 %a | 68 ret i16 %a |
33 } | 69 } |
34 | 70 |
35 define i16 @ret6(i16 %a) nounwind uwtable ssp { | 71 define i16 @ret6(i16 %a) nounwind uwtable ssp { |
36 entry: | 72 entry: |
37 ; ELF64: ret6 | 73 ; ELF64-LABEL: ret6 |
38 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 | 74 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 |
39 ; ELF64: blr | 75 ; ELF64: blr |
40 ret i16 %a | 76 ret i16 %a |
41 } | 77 } |
42 | 78 |
43 define signext i32 @ret7(i32 signext %a) nounwind uwtable ssp { | 79 define signext i32 @ret7(i32 signext %a) nounwind uwtable ssp { |
44 entry: | 80 entry: |
45 ; ELF64: ret7 | 81 ; ELF64-LABEL: ret7 |
46 ; ELF64: extsw | 82 ; ELF64: extsw |
47 ; ELF64: blr | 83 ; ELF64: blr |
48 ret i32 %a | 84 ret i32 %a |
49 } | 85 } |
50 | 86 |
51 define zeroext i32 @ret8(i32 signext %a) nounwind uwtable ssp { | 87 define zeroext i32 @ret8(i32 signext %a) nounwind uwtable ssp { |
52 entry: | 88 entry: |
53 ; ELF64: ret8 | 89 ; ELF64-LABEL: ret8 |
54 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32 | 90 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32 |
55 ; ELF64: blr | 91 ; ELF64: blr |
56 ret i32 %a | 92 ret i32 %a |
57 } | 93 } |
58 | 94 |
59 define i32 @ret9(i32 %a) nounwind uwtable ssp { | 95 define i32 @ret9(i32 %a) nounwind uwtable ssp { |
60 entry: | 96 entry: |
61 ; ELF64: ret9 | 97 ; ELF64-LABEL: ret9 |
62 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32 | 98 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32 |
63 ; ELF64: blr | 99 ; ELF64: blr |
64 ret i32 %a | 100 ret i32 %a |
65 } | 101 } |
66 | 102 |
67 define i64 @ret10(i64 %a) nounwind uwtable ssp { | 103 define i64 @ret10(i64 %a) nounwind uwtable ssp { |
68 entry: | 104 entry: |
69 ; ELF64: ret10 | 105 ; ELF64-LABEL: ret10 |
70 ; ELF64-NOT: exts | 106 ; ELF64-NOT: exts |
71 ; ELF64-NOT: rldicl | 107 ; ELF64-NOT: rldicl |
72 ; ELF64: blr | 108 ; ELF64: blr |
73 ret i64 %a | 109 ret i64 %a |
74 } | 110 } |
75 | 111 |
76 define float @ret11(float %a) nounwind uwtable ssp { | 112 define float @ret11(float %a) nounwind uwtable ssp { |
77 entry: | 113 entry: |
78 ; ELF64: ret11 | 114 ; ELF64-LABEL: ret11 |
79 ; ELF64: blr | 115 ; ELF64: blr |
80 ret float %a | 116 ret float %a |
81 } | 117 } |
82 | 118 |
83 define double @ret12(double %a) nounwind uwtable ssp { | 119 define double @ret12(double %a) nounwind uwtable ssp { |
84 entry: | 120 entry: |
85 ; ELF64: ret12 | 121 ; ELF64-LABEL: ret12 |
86 ; ELF64: blr | 122 ; ELF64: blr |
87 ret double %a | 123 ret double %a |
88 } | 124 } |
89 | 125 |
90 define i8 @ret13() nounwind uwtable ssp { | 126 define i8 @ret13() nounwind uwtable ssp { |
91 entry: | 127 entry: |
92 ; ELF64: ret13 | 128 ; ELF64-LABEL: ret13 |
93 ; ELF64: li | 129 ; ELF64: li |
94 ; ELF64: blr | 130 ; ELF64: blr |
95 ret i8 15; | 131 ret i8 15; |
96 } | 132 } |
97 | 133 |
98 define i16 @ret14() nounwind uwtable ssp { | 134 define i16 @ret14() nounwind uwtable ssp { |
99 entry: | 135 entry: |
100 ; ELF64: ret14 | 136 ; ELF64-LABEL: ret14 |
101 ; ELF64: li | 137 ; ELF64: li |
102 ; ELF64: blr | 138 ; ELF64: blr |
103 ret i16 -225; | 139 ret i16 -225; |
104 } | 140 } |
105 | 141 |
106 define i32 @ret15() nounwind uwtable ssp { | 142 define i32 @ret15() nounwind uwtable ssp { |
107 entry: | 143 entry: |
108 ; ELF64: ret15 | 144 ; ELF64-LABEL: ret15 |
109 ; ELF64: lis | 145 ; ELF64: lis |
110 ; ELF64: ori | 146 ; ELF64: ori |
111 ; ELF64: blr | 147 ; ELF64: blr |
112 ret i32 278135; | 148 ret i32 278135; |
113 } | 149 } |
114 | 150 |
115 define i64 @ret16() nounwind uwtable ssp { | 151 define i64 @ret16() nounwind uwtable ssp { |
116 entry: | 152 entry: |
117 ; ELF64: ret16 | 153 ; ELF64-LABEL: ret16 |
118 ; ELF64: li | 154 ; ELF64: li |
119 ; ELF64: sldi | 155 ; ELF64: sldi |
120 ; ELF64: oris | 156 ; ELF64: oris |
121 ; ELF64: ori | 157 ; ELF64: ori |
122 ; ELF64: blr | 158 ; ELF64: blr |
123 ret i64 27813515225; | 159 ret i64 27813515225; |
124 } | 160 } |
125 | 161 |
126 define float @ret17() nounwind uwtable ssp { | 162 define float @ret17() nounwind uwtable ssp { |
127 entry: | 163 entry: |
128 ; ELF64: ret17 | 164 ; ELF64-LABEL: ret17 |
129 ; ELF64: addis | 165 ; ELF64: addis |
130 ; ELF64: lfs | 166 ; ELF64: lfs |
131 ; ELF64: blr | 167 ; ELF64: blr |
132 ret float 2.5; | 168 ret float 2.5; |
133 } | 169 } |
134 | 170 |
135 define double @ret18() nounwind uwtable ssp { | 171 define double @ret18() nounwind uwtable ssp { |
136 entry: | 172 entry: |
137 ; ELF64: ret18 | 173 ; ELF64-LABEL: ret18 |
138 ; ELF64: addis | 174 ; ELF64: addis |
139 ; ELF64: lfd | 175 ; ELF64: lfd |
140 ; ELF64: blr | 176 ; ELF64: blr |
141 ret double 2.5e-33; | 177 ret double 2.5e-33; |
142 } | 178 } |