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comparison test/CodeGen/R600/operand-spacing.ll @ 83:60c9769439b8 LLVM3.7

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LLVM 3.7
author Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
date Wed, 18 Feb 2015 14:55:36 +0900
parents 54457678186b
children
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78:af83660cff7b 83:60c9769439b8
1 ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI %s 1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=GCN %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=VI -check-prefix=GCN %s
2 3
3 ; Make sure there isn't an extra space between the instruction name and first operands. 4 ; Make sure there isn't an extra space between the instruction name and first operands.
4 5
5 ; SI-LABEL: @add_f32 6 ; GCN-LABEL: {{^}}add_f32:
6 ; SI-DAG: S_LOAD_DWORD [[SREGA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb 7 ; SI-DAG: s_load_dword [[SREGA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
7 ; SI-DAG: S_LOAD_DWORD [[SREGB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc 8 ; SI-DAG: s_load_dword [[SREGB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
8 ; SI: V_MOV_B32_e32 [[VREGB:v[0-9]+]], [[SREGB]] 9 ; VI-DAG: s_load_dword [[SREGA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
9 ; SI: V_ADD_F32_e32 [[RESULT:v[0-9]+]], [[SREGA]], [[VREGB]] 10 ; VI-DAG: s_load_dword [[SREGB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
10 ; SI: BUFFER_STORE_DWORD [[RESULT]], 11 ; GCN: v_mov_b32_e32 [[VREGB:v[0-9]+]], [[SREGB]]
12 ; GCN: v_add_f32_e32 [[RESULT:v[0-9]+]], [[SREGA]], [[VREGB]]
13 ; GCN: buffer_store_dword [[RESULT]],
11 define void @add_f32(float addrspace(1)* %out, float %a, float %b) { 14 define void @add_f32(float addrspace(1)* %out, float %a, float %b) {
12 %result = fadd float %a, %b 15 %result = fadd float %a, %b
13 store float %result, float addrspace(1)* %out 16 store float %result, float addrspace(1)* %out
14 ret void 17 ret void
15 } 18 }