comparison test/CodeGen/X86/win_cst_pool.ll @ 83:60c9769439b8 LLVM3.7

LLVM 3.7
author Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
date Wed, 18 Feb 2015 14:55:36 +0900
parents 54457678186b
children afa8332a0e37
comparison
equal deleted inserted replaced
78:af83660cff7b 83:60c9769439b8
1 ; RUN: llc < %s -mtriple=x86_64-win32 -mcpu=corei7 | FileCheck %s 1 ; RUN: llc < %s -mtriple=x86_64-win32 -mattr=sse2 | FileCheck %s
2 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" 2 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
3 target triple = "x86_64-pc-windows-msvc" 3 target triple = "x86_64-pc-windows-msvc"
4 4
5 define double @double() { 5 define double @double() {
6 ret double 0x0000000000800000 6 ret double 0x0000000000800000
7 } 7 }
8 ; CHECK: .globl __real@0000000000800000 8 ; CHECK: .globl __real@0000000000800000
9 ; CHECK-NEXT: .section .rdata,"rd",discard,__real@0000000000800000 9 ; CHECK-NEXT: .section .rdata,"dr",discard,__real@0000000000800000
10 ; CHECK-NEXT: .align 8 10 ; CHECK-NEXT: .align 8
11 ; CHECK-NEXT: __real@0000000000800000: 11 ; CHECK-NEXT: __real@0000000000800000:
12 ; CHECK-NEXT: .quad 8388608 12 ; CHECK-NEXT: .quad 8388608
13 ; CHECK: double: 13 ; CHECK: double:
14 ; CHECK: movsd __real@0000000000800000(%rip), %xmm0 14 ; CHECK: movsd __real@0000000000800000(%rip), %xmm0
16 16
17 define <4 x i32> @vec1() { 17 define <4 x i32> @vec1() {
18 ret <4 x i32> <i32 3, i32 2, i32 1, i32 0> 18 ret <4 x i32> <i32 3, i32 2, i32 1, i32 0>
19 } 19 }
20 ; CHECK: .globl __xmm@00000000000000010000000200000003 20 ; CHECK: .globl __xmm@00000000000000010000000200000003
21 ; CHECK-NEXT: .section .rdata,"rd",discard,__xmm@00000000000000010000000200000003 21 ; CHECK-NEXT: .section .rdata,"dr",discard,__xmm@00000000000000010000000200000003
22 ; CHECK-NEXT: .align 16 22 ; CHECK-NEXT: .align 16
23 ; CHECK-NEXT: __xmm@00000000000000010000000200000003: 23 ; CHECK-NEXT: __xmm@00000000000000010000000200000003:
24 ; CHECK-NEXT: .long 3 24 ; CHECK-NEXT: .long 3
25 ; CHECK-NEXT: .long 2 25 ; CHECK-NEXT: .long 2
26 ; CHECK-NEXT: .long 1 26 ; CHECK-NEXT: .long 1
31 31
32 define <8 x i16> @vec2() { 32 define <8 x i16> @vec2() {
33 ret <8 x i16> <i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0> 33 ret <8 x i16> <i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>
34 } 34 }
35 ; CHECK: .globl __xmm@00000001000200030004000500060007 35 ; CHECK: .globl __xmm@00000001000200030004000500060007
36 ; CHECK-NEXT: .section .rdata,"rd",discard,__xmm@00000001000200030004000500060007 36 ; CHECK-NEXT: .section .rdata,"dr",discard,__xmm@00000001000200030004000500060007
37 ; CHECK-NEXT: .align 16 37 ; CHECK-NEXT: .align 16
38 ; CHECK-NEXT: __xmm@00000001000200030004000500060007: 38 ; CHECK-NEXT: __xmm@00000001000200030004000500060007:
39 ; CHECK-NEXT: .short 7 39 ; CHECK-NEXT: .short 7
40 ; CHECK-NEXT: .short 6 40 ; CHECK-NEXT: .short 6
41 ; CHECK-NEXT: .short 5 41 ; CHECK-NEXT: .short 5
51 51
52 define <4 x float> @undef1() { 52 define <4 x float> @undef1() {
53 ret <4 x float> <float 1.0, float 1.0, float undef, float undef> 53 ret <4 x float> <float 1.0, float 1.0, float undef, float undef>
54 54
55 ; CHECK: .globl __xmm@00000000000000003f8000003f800000 55 ; CHECK: .globl __xmm@00000000000000003f8000003f800000
56 ; CHECK-NEXT: .section .rdata,"rd",discard,__xmm@00000000000000003f8000003f800000 56 ; CHECK-NEXT: .section .rdata,"dr",discard,__xmm@00000000000000003f8000003f800000
57 ; CHECK-NEXT: .align 16 57 ; CHECK-NEXT: .align 16
58 ; CHECK-NEXT: __xmm@00000000000000003f8000003f800000: 58 ; CHECK-NEXT: __xmm@00000000000000003f8000003f800000:
59 ; CHECK-NEXT: .long 1065353216 # float 1 59 ; CHECK-NEXT: .long 1065353216 # float 1
60 ; CHECK-NEXT: .long 1065353216 # float 1 60 ; CHECK-NEXT: .long 1065353216 # float 1
61 ; CHECK-NEXT: .zero 4 61 ; CHECK-NEXT: .zero 4