CbC/CbC_llvm: lib/Target/ARM/ARMAsmPrinter.cpp comparison

comparison lib/Target/ARM/ARMAsmPrinter.cpp @ 148:63bd29f05246

merged

author	Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date	Wed, 14 Aug 2019 19:46:37 +0900
parents	c2174574ed3a
children

comparison

equal deleted inserted replaced

-:3fc4d5c3e21e
+:63bd29f05246
 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
 //
-//                     The LLVM Compiler Infrastructure
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-//
+// See https://llvm.org/LICENSE.txt for license information.
-// This file is distributed under the University of Illinois Open Source
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains a printer that converts from our internal representation
 // of machine-dependent LLVM code to GAS-format ARM assembly language.
 #include "ARM.h"
 #include "ARMConstantPoolValue.h"
 #include "ARMMachineFunctionInfo.h"
 #include "ARMTargetMachine.h"
 #include "ARMTargetObjectFile.h"
-#include "InstPrinter/ARMInstPrinter.h"
 #include "MCTargetDesc/ARMAddressingModes.h"
+#include "MCTargetDesc/ARMInstPrinter.h"
 #include "MCTargetDesc/ARMMCExpr.h"
+#include "TargetInfo/ARMTargetInfo.h"
 #include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/SmallString.h"
 #include "llvm/BinaryFormat/COFF.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineJumpTableInfo.h"
 // Collect all globals that had their storage promoted to a constant pool.
 // Functions are emitted before variables, so this accumulates promoted
 // globals from all functions in PromotedGlobals.
 for (auto *GV : AFI->getGlobalsPromotedToConstantPool())
 PromotedGlobals.insert(GV);
 // Calculate this function's optimization goal.
 unsigned OptimizationGoal;
-if (F.hasFnAttribute(Attribute::OptimizeNone))
+if (F.hasOptNone())
 // For best debugging illusion, speed and small size sacrificed
 OptimizationGoal = 6;
-else if (F.optForMinSize())
+else if (F.hasMinSize())
 // Aggressively for small size, speed and debug illusion sacrificed
 OptimizationGoal = 4;
-else if (F.optForSize())
+else if (F.hasOptSize())
 // For small size, but speed and debugging illusion preserved
 OptimizationGoal = 3;
 else if (TM.getOptLevel() == CodeGenOpt::Aggressive)
 // Aggressively for speed, small size and debug illusion sacrificed
 OptimizationGoal = 2;
 // We didn't modify anything.
 return false;
 }
+void ARMAsmPrinter::PrintSymbolOperand(const MachineOperand &MO,
+raw_ostream &O) {
+assert(MO.isGlobal() && "caller should check MO.isGlobal");
+unsigned TF = MO.getTargetFlags();
+if (TF & ARMII::MO_LO16)
+O << ":lower16:";
+else if (TF & ARMII::MO_HI16)
+O << ":upper16:";
+GetARMGVSymbol(MO.getGlobal(), TF)->print(O, MAI);
+printOffset(MO.getOffset(), O);
+}
 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
 raw_ostream &O) {
 const MachineOperand &MO = MI->getOperand(OpNum);
-unsigned TF = MO.getTargetFlags();
 switch (MO.getType()) {
 default: llvm_unreachable("<unknown operand type>");
 case MachineOperand::MO_Register: {
 unsigned Reg = MO.getReg();
-assert(TargetRegisterInfo::isPhysicalRegister(Reg));
+assert(Register::isPhysicalRegister(Reg));
 assert(!MO.getSubReg() && "Subregs should be eliminated!");
 if(ARM::GPRPairRegClass.contains(Reg)) {
 const MachineFunction &MF = *MI->getParent()->getParent();
 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
 }
 O << ARMInstPrinter::getRegisterName(Reg);
 break;
 }
 case MachineOperand::MO_Immediate: {
-int64_t Imm = MO.getImm();
 O << '#';
+unsigned TF = MO.getTargetFlags();
 if (TF == ARMII::MO_LO16)
 O << ":lower16:";
 else if (TF == ARMII::MO_HI16)
 O << ":upper16:";
-O << Imm;
+O << MO.getImm();
 break;
 }
 case MachineOperand::MO_MachineBasicBlock:
 MO.getMBB()->getSymbol()->print(O, MAI);
 return;
 case MachineOperand::MO_GlobalAddress: {
-const GlobalValue *GV = MO.getGlobal();
+PrintSymbolOperand(MO, O);
-if (TF & ARMII::MO_LO16)
-O << ":lower16:";
-else if (TF & ARMII::MO_HI16)
-O << ":upper16:";
-GetARMGVSymbol(GV, TF)->print(O, MAI);
-printOffset(MO.getOffset(), O);
 break;
 }
 case MachineOperand::MO_ConstantPoolIndex:
 if (Subtarget->genExecuteOnly())
 llvm_unreachable("execute-only should not generate constant pools");
 GetCPISymbol(MO.getIndex())->print(O, MAI);
 break;
 }
+}
+MCSymbol *ARMAsmPrinter::GetCPISymbol(unsigned CPID) const {
+// The AsmPrinter::GetCPISymbol superclass method tries to use CPID as
+// indexes in MachineConstantPool, which isn't in sync with indexes used here.
+const DataLayout &DL = getDataLayout();
+return OutContext.getOrCreateSymbol(Twine(DL.getPrivateGlobalPrefix()) +
+"CPI" + Twine(getFunctionNumber()) + "_" +
+Twine(CPID));
 }
 //===--------------------------------------------------------------------===//
 MCSymbol *ARMAsmPrinter::
 << getFunctionNumber() << '_' << uid;
 return OutContext.getOrCreateSymbol(Name);
 }
 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
-unsigned AsmVariant, const char *ExtraCode,
+const char *ExtraCode, raw_ostream &O) {
-raw_ostream &O) {
 // Does this asm operand have a single letter operand modifier?
 if (ExtraCode && ExtraCode[0]) {
 if (ExtraCode[1] != 0) return true; // Unknown modifier.
 switch (ExtraCode[0]) {
 default:
 // See if this is a generic print operand
-return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
+return AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O);
-case 'a': // Print as a memory address.
-if (MI->getOperand(OpNum).isReg()) {
-O << "["
-<< ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
-<< "]";
-return false;
-}
-LLVM_FALLTHROUGH;
-case 'c': // Don't print "#" before an immediate operand.
-if (!MI->getOperand(OpNum).isImm())
-return true;
-O << MI->getOperand(OpNum).getImm();
-return false;
 case 'P': // Print a VFP double precision register.
 case 'q': // Print a NEON quad precision register.
 printOperand(MI, OpNum, O);
 return false;
 case 'y': // Print a VFP single precision register as indexed double.
 OpNum += 1;
 }
 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
 unsigned RC;
-InlineAsm::hasRegClassConstraint(Flags, RC);
+bool FirstHalf;
-if (RC == ARM::GPRPairRegClassID) {
+const ARMBaseTargetMachine &ATM =
+static_cast<const ARMBaseTargetMachine &>(TM);
+// 'Q' should correspond to the low order register and 'R' to the high
+// order register.  Whether this corresponds to the upper or lower half
+// depends on the endianess mode.
+if (ExtraCode[0] == 'Q')
+FirstHalf = ATM.isLittleEndian();
+else
+// ExtraCode[0] == 'R'.
+FirstHalf = !ATM.isLittleEndian();
+const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
+if (InlineAsm::hasRegClassConstraint(Flags, RC) &&
+ARM::GPRPairRegClass.hasSubClassEq(TRI->getRegClass(RC))) {
 if (NumVals != 1)
 return true;
 const MachineOperand &MO = MI->getOperand(OpNum);
 if (!MO.isReg())
 return true;
 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
-unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
+unsigned Reg = TRI->getSubReg(MO.getReg(), FirstHalf ?
 ARM::gsub_0 : ARM::gsub_1);
 O << ARMInstPrinter::getRegisterName(Reg);
 return false;
 }
 if (NumVals != 2)
 return true;
-unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
+unsigned RegOp = FirstHalf ? OpNum : OpNum + 1;
 if (RegOp >= MI->getNumOperands())
 return true;
 const MachineOperand &MO = MI->getOperand(RegOp);
 if (!MO.isReg())
 return true;
 printOperand(MI, OpNum, O);
 return false;
 }
 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
-unsigned OpNum, unsigned AsmVariant,
+unsigned OpNum, const char *ExtraCode,
-const char *ExtraCode,
 raw_ostream &O) {
 // Does this asm operand have a single letter operand modifier?
 if (ExtraCode && ExtraCode[0]) {
 if (ExtraCode[1] != 0) return true; // Unknown modifier.
 ARMBuildAttrs::PositiveZero);
 else if (!TM.Options.UnsafeFPMath)
 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
 ARMBuildAttrs::IEEEDenormals);
 else {
-if (!STI.hasVFP2()) {
+if (!STI.hasVFP2Base()) {
 // When the target doesn't have an FPU (by design or
 // intention), the assumptions made on the software support
 // mirror that of the equivalent hardware support *if it
 // existed*. For v7 and better we indicate that denormals are
 // flushed preserving sign, and for V6 we indicate that
 // denormals are flushed to positive zero.
 if (STI.hasV7Ops())
 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
 ARMBuildAttrs::PreserveFPSign);
-} else if (STI.hasVFP3()) {
+} else if (STI.hasVFP3Base()) {
 // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
 // the sign bit of the zero matches the sign bit of the input or
 // result that is being flushed to zero.
 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
 ARMBuildAttrs::PreserveFPSign);
 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
 ARMBuildAttrs::R9IsGPR);
 }
 //===----------------------------------------------------------------------===//
+static MCSymbol *getBFLabel(StringRef Prefix, unsigned FunctionNumber,
+unsigned LabelId, MCContext &Ctx) {
+MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
++ "BF" + Twine(FunctionNumber) + "_" + Twine(LabelId));
+return Label;
+}
 static MCSymbol *getPICLabel(StringRef Prefix, unsigned FunctionNumber,
 unsigned LabelId, MCContext &Ctx) {
 MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
 return MCSym;
 } else if (Subtarget->isTargetCOFF()) {
 assert(Subtarget->isTargetWindows() &&
 "Windows is the only supported COFF target");
-bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
+bool IsIndirect =
+(TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB));
 if (!IsIndirect)
 return getSymbol(GV);
 SmallString<128> Name;
-Name = "__imp_";
+if (TargetFlags & ARMII::MO_DLLIMPORT)
+Name = "__imp_";
+else if (TargetFlags & ARMII::MO_COFFSTUB)
+Name = ".refptr.";
 getNameWithPrefix(Name, GV);
-return OutContext.getOrCreateSymbol(Name);
+MCSymbol *MCSym = OutContext.getOrCreateSymbol(Name);
+if (TargetFlags & ARMII::MO_COFFSTUB) {
+MachineModuleInfoCOFF &MMICOFF =
+MMI->getObjFileInfo<MachineModuleInfoCOFF>();
+MachineModuleInfoImpl::StubValueTy &StubSym =
+MMICOFF.getGVStubEntry(MCSym);
+if (!StubSym.getPointer())
+StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV), true);
+}
+return MCSym;
 } else if (Subtarget->isTargetELF()) {
 return getSymbol(GV);
 }
 llvm_unreachable("unexpected target");
 }
 const MachineOperand &MO1 = MI->getOperand(1);
 unsigned JTI = MO1.getIndex();
 if (Subtarget->isThumb1Only())
 EmitAlignment(2);
 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
 OutStreamer->EmitLabel(JTISymbol);
 // Emit each entry of the table.
 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
 "Only instruction which are involved into frame setup code are allowed");
 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
 const MachineFunction &MF = *MI->getParent()->getParent();
-const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
+const TargetRegisterInfo *TargetRegInfo =
-const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
+MF.getSubtarget().getRegisterInfo();
+const MachineRegisterInfo &MachineRegInfo = MF.getRegInfo();
-unsigned FramePtr = RegInfo->getFrameRegister(MF);
+unsigned FramePtr = TargetRegInfo->getFrameRegister(MF);
 unsigned Opc = MI->getOpcode();
 unsigned SrcReg, DstReg;
 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
 // Two special cases:
 // restored when unwinding, because the function can modify the
 // corresponding stack slots.
 if (MO.isUndef()) {
 assert(RegList.empty() &&
 "Pad registers must come before restored ones");
-Pad += 4;
+unsigned Width =
+TargetRegInfo->getRegSizeInBits(MO.getReg(), MachineRegInfo) / 8;
+Pad += Width;
 continue;
 }
-RegList.push_back(MO.getReg());
+// Check for registers that are remapped (for a Thumb1 prologue that
+// saves high registers).
+unsigned Reg = MO.getReg();
+if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(Reg))
+Reg = RemappedReg;
+RegList.push_back(Reg);
 }
 break;
 case ARM::STR_PRE_IMM:
 case ARM::STR_PRE_REG:
 case ARM::t2STR_PRE:
 // Grab the constpool index and check, whether it corresponds to
 // original or cloned constpool entry.
 unsigned CPI = MI->getOperand(1).getIndex();
 const MachineConstantPool *MCP = MF.getConstantPool();
 if (CPI >= MCP->getConstants().size())
-CPI = AFI.getOriginalCPIdx(CPI);
+CPI = AFI->getOriginalCPIdx(CPI);
 assert(CPI != -1U && "Invalid constpool index");
 // Derive the actual offset.
 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
 }
 }
 } else if (DstReg == ARM::SP) {
 MI->print(errs());
 llvm_unreachable("Unsupported opcode for unwinding information");
-}
+} else if (Opc == ARM::tMOVr) {
-else {
+// If a Thumb1 function spills r8-r11, we copy the values to low
+// registers before pushing them. Record the copy so we can emit the
+// correct ".save" later.
+AFI->EHPrologueRemappedRegs[DstReg] = SrcReg;
+} else {
 MI->print(errs());
 llvm_unreachable("Unsupported opcode for unwinding information");
 }
 }
 }
 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
 TmpInst.addOperand(MCOperand::createReg(0));
 // Add 's' bit operand (always reg0 for this)
 TmpInst.addOperand(MCOperand::createReg(0));
 EmitToStreamer(*OutStreamer, TmpInst);
+return;
+}
+case ARM::t2BFi:
+case ARM::t2BFic:
+case ARM::t2BFLi:
+case ARM::t2BFr:
+case ARM::t2BFLr: {
+// This is a Branch Future instruction.
+const MCExpr *BranchLabel = MCSymbolRefExpr::create(
+getBFLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
+MI->getOperand(0).getIndex(), OutContext),
+OutContext);
+auto MCInst = MCInstBuilder(Opc).addExpr(BranchLabel);
+if (MI->getOperand(1).isReg()) {
+// For BFr/BFLr
+MCInst.addReg(MI->getOperand(1).getReg());
+} else {
+// For BFi/BFLi/BFic
+const MCExpr *BranchTarget;
+if (MI->getOperand(1).isMBB())
+BranchTarget = MCSymbolRefExpr::create(
+MI->getOperand(1).getMBB()->getSymbol(), OutContext);
+else if (MI->getOperand(1).isGlobal()) {
+const GlobalValue *GV = MI->getOperand(1).getGlobal();
+BranchTarget = MCSymbolRefExpr::create(
+GetARMGVSymbol(GV, MI->getOperand(1).getTargetFlags()), OutContext);
+} else if (MI->getOperand(1).isSymbol()) {
+BranchTarget = MCSymbolRefExpr::create(
+GetExternalSymbolSymbol(MI->getOperand(1).getSymbolName()),
+OutContext);
+} else
+llvm_unreachable("Unhandled operand kind in Branch Future instruction");
+MCInst.addExpr(BranchTarget);
+}
+if (Opc == ARM::t2BFic) {
+const MCExpr *ElseLabel = MCSymbolRefExpr::create(
+getBFLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
+MI->getOperand(2).getIndex(), OutContext),
+OutContext);
+MCInst.addExpr(ElseLabel);
+MCInst.addImm(MI->getOperand(3).getImm());
+} else {
+MCInst.addImm(MI->getOperand(2).getImm())
+.addReg(MI->getOperand(3).getReg());
+}
+EmitToStreamer(*OutStreamer, MCInst);
+return;
+}
+case ARM::t2BF_LabelPseudo: {
+// This is a pseudo op for a label used by a branch future instruction
+// Emit the label.
+OutStreamer->EmitLabel(getBFLabel(DL.getPrivateGlobalPrefix(),
+getFunctionNumber(),
+MI->getOperand(0).getIndex(), OutContext));
 return;
 }
 case ARM::tPICADD: {
 // This is a pseudo op for a label + instruction sequence, which looks like:
 // LPC0:

Mercurial > hg > CbC > CbC_llvm

comparison lib/Target/ARM/ARMAsmPrinter.cpp @ 148:63bd29f05246