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comparison lib/Target/AVR/AVRISelLowering.h @ 148:63bd29f05246

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merged
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 14 Aug 2019 19:46:37 +0900
parents c2174574ed3a
children
comparison
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146:3fc4d5c3e21e 148:63bd29f05246
1 //===-- AVRISelLowering.h - AVR DAG Lowering Interface ----------*- C++ -*-===// 1 //===-- AVRISelLowering.h - AVR DAG Lowering Interface ----------*- C++ -*-===//
2 // 2 //
3 // The LLVM Compiler Infrastructure 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // 4 // See https://llvm.org/LICENSE.txt for license information.
5 // This file is distributed under the University of Illinois Open Source 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 // License. See LICENSE.TXT for details.
7 // 6 //
8 //===----------------------------------------------------------------------===// 7 //===----------------------------------------------------------------------===//
9 // 8 //
10 // This file defines the interfaces that AVR uses to lower LLVM code into a 9 // This file defines the interfaces that AVR uses to lower LLVM code into a
11 // selection DAG. 10 // selection DAG.
62 SELECT_CC 61 SELECT_CC
63 }; 62 };
64 63
65 } // end of namespace AVRISD 64 } // end of namespace AVRISD
66 65
66 class AVRSubtarget;
67 class AVRTargetMachine; 67 class AVRTargetMachine;
68 68
69 /// Performs target lowering for the AVR. 69 /// Performs target lowering for the AVR.
70 class AVRTargetLowering : public TargetLowering { 70 class AVRTargetLowering : public TargetLowering {
71 public: 71 public:
72 explicit AVRTargetLowering(AVRTargetMachine &TM); 72 explicit AVRTargetLowering(const AVRTargetMachine &TM,
73 const AVRSubtarget &STI);
73 74
74 public: 75 public:
75 MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override { 76 MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override {
76 return MVT::i8; 77 return MVT::i8;
77 } 78 }
125 SelectionDAG &DAG) const override; 126 SelectionDAG &DAG) const override;
126 127
127 unsigned getRegisterByName(const char* RegName, EVT VT, 128 unsigned getRegisterByName(const char* RegName, EVT VT,
128 SelectionDAG &DAG) const override; 129 SelectionDAG &DAG) const override;
129 130
131 bool shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout &DL)
132 const override {
133 return false;
134 }
135
130 private: 136 private:
131 SDValue getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AVRcc, 137 SDValue getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AVRcc,
132 SelectionDAG &DAG, SDLoc dl) const; 138 SelectionDAG &DAG, SDLoc dl) const;
133 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const; 139 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
134 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const; 140 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
162 CallingConv::ID CallConv, bool isVarArg, 168 CallingConv::ID CallConv, bool isVarArg,
163 const SmallVectorImpl<ISD::InputArg> &Ins, 169 const SmallVectorImpl<ISD::InputArg> &Ins,
164 const SDLoc &dl, SelectionDAG &DAG, 170 const SDLoc &dl, SelectionDAG &DAG,
165 SmallVectorImpl<SDValue> &InVals) const; 171 SmallVectorImpl<SDValue> &InVals) const;
166 172
173 protected:
174
175 const AVRSubtarget &Subtarget;
176
167 private: 177 private:
168 MachineBasicBlock *insertShift(MachineInstr &MI, MachineBasicBlock *BB) const; 178 MachineBasicBlock *insertShift(MachineInstr &MI, MachineBasicBlock *BB) const;
169 MachineBasicBlock *insertMul(MachineInstr &MI, MachineBasicBlock *BB) const; 179 MachineBasicBlock *insertMul(MachineInstr &MI, MachineBasicBlock *BB) const;
170 }; 180 };
171 181