CbC/CbC_llvm: lib/Target/Hexagon/HexagonNewValueJump.cpp comparison

comparison lib/Target/Hexagon/HexagonNewValueJump.cpp @ 148:63bd29f05246

merged

author	Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date	Wed, 14 Aug 2019 19:46:37 +0900
parents	c2174574ed3a
children

comparison

equal deleted inserted replaced

-:3fc4d5c3e21e
+:63bd29f05246
 //===- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -----------===//
 //
-//                     The LLVM Compiler Infrastructure
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-//
+// See https://llvm.org/LICENSE.txt for license information.
-// This file is distributed under the University of Illinois Open Source
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This implements NewValueJump pass in Hexagon.
 // Ideally, we should merge this as a Peephole pass prior to register
 // Having said that, we should re-attempt to pull this earlier at some point
 // in future.
 // The basic approach looks for sequence of predicated jump, compare instruciton
 // that genereates the predicate and, the feeder to the predicate. Once it finds
-// all, it collapses compare and jump instruction into a new valu jump
+// all, it collapses compare and jump instruction into a new value jump
 // intstructions.
 //
 //===----------------------------------------------------------------------===//
 #include "Hexagon.h"
 #include "HexagonInstrInfo.h"
 #include "HexagonRegisterInfo.h"
+#include "HexagonSubtarget.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 private:
 const HexagonInstrInfo *QII;
 const HexagonRegisterInfo *QRI;
-/// \brief A handle to the branch probability pass.
+/// A handle to the branch probability pass.
 const MachineBranchProbabilityInfo *MBPI;
 bool isNewValueJumpCandidate(const MachineInstr &MI) const;
 };
 if (!Hexagon::IntRegsRegClass.contains(Op.getReg()))
 return false;
 }
 assert(HadDef);
-// Make sure there there is no 'def' or 'use' of any of the uses of
+// Make sure there is no 'def' or 'use' of any of the uses of
-// feeder insn between it's definition, this MI and jump, jmpInst
+// feeder insn between its definition, this MI and jump, jmpInst
 // skipping compare, cmpInst.
 // Here's the example.
 //    r21=memub(r22+r24<<#0)
 //    p0 = cmp.eq(r21, #0)
 //    r4=memub(r3+r21<<#0)
 // If the same register appears as both operands, we cannot generate a new
 // value compare. Only one operand may use the .new suffix.
 if (cmpReg1 == cmpOp2)
 return false;
-// Make sure that that second register is not from COPY
+// Make sure that the second register is not from COPY
-// At machine code level, we don't need this, but if we decide
+// at machine code level, we don't need this, but if we decide
 // to move new value jump prior to RA, we would be needing this.
 MachineRegisterInfo &MRI = MF.getRegInfo();
-if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) {
+if (secondReg && !Register::isPhysicalRegister(cmpOp2)) {
 MachineInstr *def = MRI.getVRegDef(cmpOp2);
 if (def->getOpcode() == TargetOpcode::COPY)
 return false;
 }
 }
 // Walk the instructions after the compare (predicate def) to the jump,
 // and satisfy the following conditions.
 ++II;
 for (MachineBasicBlock::iterator localII = II; localII != end; ++localII) {
-if (localII->isDebugValue())
+if (localII->isDebugInstr())
 continue;
 // Check 1.
 // If "common" checks fail, bail out.
 if (!commonChecksToProhibitNewValueJump(optLocation, localII))
 return false;
 }
 }
 bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
-DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
+LLVM_DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
 << "********** Function: " << MF.getName() << "\n");
 if (skipFunction(MF.getFunction()))
 return false;
 // If we move NewValueJump before register allocation we'll need live variable
 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
 QRI = static_cast<const HexagonRegisterInfo *>(
 MF.getSubtarget().getRegisterInfo());
 MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
-if (DisableNewValueJumps) {
+if (DisableNewValueJumps ||
-return false;
+!MF.getSubtarget<HexagonSubtarget>().useNewValueJumps())
-}
+return false;
 int nvjCount = DbgNVJCount;
 int nvjGenerated = 0;
 // Loop through all the bb's of the function
 for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
 MBBb != MBBe; ++MBBb) {
 MachineBasicBlock *MBB = &*MBBb;
-DEBUG(dbgs() << "** dumping bb ** " << MBB->getNumber() << "\n");
+LLVM_DEBUG(dbgs() << "** dumping bb ** " << MBB->getNumber() << "\n");
-DEBUG(MBB->dump());
+LLVM_DEBUG(MBB->dump());
-DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n");
+LLVM_DEBUG(dbgs() << "\n"
+<< "********** dumping instr bottom up **********\n");
 bool foundJump    = false;
 bool foundCompare = false;
 bool invertPredicate = false;
 unsigned predReg = 0; // predicate reg of the jump.
 unsigned cmpReg1 = 0;
 bool isSecondOpNewified = false;
 // Traverse the basic block - bottom up
 for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
 MII != E;) {
 MachineInstr &MI = *--MII;
-if (MI.isDebugValue()) {
+if (MI.isDebugInstr()) {
 continue;
 }
 if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated))
 break;
-DEBUG(dbgs() << "Instr: "; MI.dump(); dbgs() << "\n");
+LLVM_DEBUG(dbgs() << "Instr: "; MI.dump(); dbgs() << "\n");
 if (!foundJump && (MI.getOpcode() == Hexagon::J2_jumpt ||
 MI.getOpcode() == Hexagon::J2_jumptpt ||
 MI.getOpcode() == Hexagon::J2_jumpf ||
 MI.getOpcode() == Hexagon::J2_jumpfpt ||
 // This is where you would insert your compare and
 // instr that feeds compare
 jmpPos = MII;
 jmpInstr = &MI;
 predReg = MI.getOperand(0).getReg();
-afterRA = TargetRegisterInfo::isPhysicalRegister(predReg);
+afterRA = Register::isPhysicalRegister(predReg);
 // If ifconverter had not messed up with the kill flags of the
 // operands, the following check on the kill flag would suffice.
 // if(!jmpInstr->getOperand(0).isKill()) break;
-// This predicate register is live out out of BB
+// This predicate register is live out of BB
 // this would only work if we can actually use Live
 // variable analysis on phy regs - but LLVM does not
 // provide LV analysis on phys regs.
 //if(LVs.isLiveOut(predReg, *MBB)) break;

Mercurial > hg > CbC > CbC_llvm

comparison lib/Target/Hexagon/HexagonNewValueJump.cpp @ 148:63bd29f05246