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comparison lib/Target/Sparc/SparcTargetMachine.cpp @ 148:63bd29f05246

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merged
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 14 Aug 2019 19:46:37 +0900
parents c2174574ed3a
children
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146:3fc4d5c3e21e 148:63bd29f05246
1 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===// 1 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
2 // 2 //
3 // The LLVM Compiler Infrastructure 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // 4 // See https://llvm.org/LICENSE.txt for license information.
5 // This file is distributed under the University of Illinois Open Source 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 // License. See LICENSE.TXT for details.
7 // 6 //
8 //===----------------------------------------------------------------------===// 7 //===----------------------------------------------------------------------===//
9 // 8 //
10 // 9 //
11 //===----------------------------------------------------------------------===// 10 //===----------------------------------------------------------------------===//
12 11
13 #include "SparcTargetMachine.h" 12 #include "SparcTargetMachine.h"
14 #include "LeonPasses.h" 13 #include "LeonPasses.h"
15 #include "Sparc.h" 14 #include "Sparc.h"
16 #include "SparcTargetObjectFile.h" 15 #include "SparcTargetObjectFile.h"
16 #include "TargetInfo/SparcTargetInfo.h"
17 #include "llvm/CodeGen/Passes.h" 17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/CodeGen/TargetPassConfig.h" 18 #include "llvm/CodeGen/TargetPassConfig.h"
19 #include "llvm/IR/LegacyPassManager.h" 19 #include "llvm/IR/LegacyPassManager.h"
20 #include "llvm/Support/TargetRegistry.h" 20 #include "llvm/Support/TargetRegistry.h"
21 using namespace llvm; 21 using namespace llvm;
68 // abs64 Static Large text smaller than 2^31 bytes 68 // abs64 Static Large text smaller than 2^31 bytes
69 // pic13 PIC_ Small GOT < 2^13 bytes 69 // pic13 PIC_ Small GOT < 2^13 bytes
70 // pic32 PIC_ Medium GOT < 2^32 bytes 70 // pic32 PIC_ Medium GOT < 2^32 bytes
71 // 71 //
72 // All code models require that the text segment is smaller than 2GB. 72 // All code models require that the text segment is smaller than 2GB.
73 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM, 73 static CodeModel::Model
74 Reloc::Model RM, bool Is64Bit, 74 getEffectiveSparcCodeModel(Optional<CodeModel::Model> CM, Reloc::Model RM,
75 bool JIT) { 75 bool Is64Bit, bool JIT) {
76 if (CM) 76 if (CM) {
77 if (*CM == CodeModel::Tiny)
78 report_fatal_error("Target does not support the tiny CodeModel", false);
79 if (*CM == CodeModel::Kernel)
80 report_fatal_error("Target does not support the kernel CodeModel", false);
77 return *CM; 81 return *CM;
82 }
78 if (Is64Bit) { 83 if (Is64Bit) {
79 if (JIT) 84 if (JIT)
80 return CodeModel::Large; 85 return CodeModel::Large;
81 return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium; 86 return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
82 } 87 }
86 /// Create an ILP32 architecture model 91 /// Create an ILP32 architecture model
87 SparcTargetMachine::SparcTargetMachine( 92 SparcTargetMachine::SparcTargetMachine(
88 const Target &T, const Triple &TT, StringRef CPU, StringRef FS, 93 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
89 const TargetOptions &Options, Optional<Reloc::Model> RM, 94 const TargetOptions &Options, Optional<Reloc::Model> RM,
90 Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT, bool is64bit) 95 Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT, bool is64bit)
91 : LLVMTargetMachine( 96 : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
92 T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options, 97 getEffectiveRelocModel(RM),
93 getEffectiveRelocModel(RM), 98 getEffectiveSparcCodeModel(
94 getEffectiveCodeModel(CM, getEffectiveRelocModel(RM), is64bit, JIT), 99 CM, getEffectiveRelocModel(RM), is64bit, JIT),
95 OL), 100 OL),
96 TLOF(make_unique<SparcELFTargetObjectFile>()), 101 TLOF(make_unique<SparcELFTargetObjectFile>()),
97 Subtarget(TT, CPU, FS, *this, is64bit), is64Bit(is64bit) { 102 Subtarget(TT, CPU, FS, *this, is64bit), is64Bit(is64bit) {
98 initAsmInfo(); 103 initAsmInfo();
99 } 104 }
100 105
101 SparcTargetMachine::~SparcTargetMachine() {} 106 SparcTargetMachine::~SparcTargetMachine() {}
102 107
103 const SparcSubtarget * 108 const SparcSubtarget *
104 SparcTargetMachine::getSubtargetImpl(const Function &F) const { 109 SparcTargetMachine::getSubtargetImpl(const Function &F) const {
105 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 110 Attribute CPUAttr = F.getFnAttribute("target-cpu");
106 Attribute FSAttr = F.getFnAttribute("target-features"); 111 Attribute FSAttr = F.getFnAttribute("target-features");
107 112
108 std::string CPU = !CPUAttr.hasAttribute(Attribute::None) 113 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
117 // function, so we can enable it as a subtarget feature. 122 // function, so we can enable it as a subtarget feature.
118 bool softFloat = 123 bool softFloat =
119 F.hasFnAttribute("use-soft-float") && 124 F.hasFnAttribute("use-soft-float") &&
120 F.getFnAttribute("use-soft-float").getValueAsString() == "true"; 125 F.getFnAttribute("use-soft-float").getValueAsString() == "true";
121 126
122 if (softFloat) 127 if (softFloat)
123 FS += FS.empty() ? "+soft-float" : ",+soft-float"; 128 FS += FS.empty() ? "+soft-float" : ",+soft-float";
124 129
125 auto &I = SubtargetMap[CPU + FS]; 130 auto &I = SubtargetMap[CPU + FS];
126 if (!I) { 131 if (!I) {
127 // This needs to be done before we create a new subtarget since any 132 // This needs to be done before we create a new subtarget since any