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comparison lib/Target/X86/X86ScheduleAtom.td @ 148:63bd29f05246

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merged
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 14 Aug 2019 19:46:37 +0900
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146:3fc4d5c3e21e 148:63bd29f05246
1 //===- X86ScheduleAtom.td - X86 Atom Scheduling Definitions -*- tablegen -*-==// 1 //===- X86ScheduleAtom.td - X86 Atom Scheduling Definitions -*- tablegen -*-==//
2 // 2 //
3 // The LLVM Compiler Infrastructure 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // 4 // See https://llvm.org/LICENSE.txt for license information.
5 // This file is distributed under the University of Illinois Open Source 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 // License. See LICENSE.TXT for details.
7 // 6 //
8 //===----------------------------------------------------------------------===// 7 //===----------------------------------------------------------------------===//
9 // 8 //
10 // This file defines the itinerary class data for the Intel Atom 9 // This file defines the schedule class data for the Intel Atom
11 // in order (Saltwell-32nm/Bonnell-45nm) processors. 10 // in order (Saltwell-32nm/Bonnell-45nm) processors.
12 // 11 //
13 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===//
14 13
15 // 14 //
16 // Scheduling information derived from the "Intel 64 and IA32 Architectures 15 // Scheduling information derived from the "Intel 64 and IA32 Architectures
17 // Optimization Reference Manual", Chapter 13, Section 4. 16 // Optimization Reference Manual", Chapter 13, Section 4.
18 // Functional Units
19 // Port 0
20 def Port0 : FuncUnit; // ALU: ALU0, shift/rotate, load/store
21 // SIMD/FP: SIMD ALU, Shuffle,SIMD/FP multiply, divide
22 def Port1 : FuncUnit; // ALU: ALU1, bit processing, jump, and LEA
23 // SIMD/FP: SIMD ALU, FP Adder
24
25 def AtomItineraries : ProcessorItineraries<
26 [ Port0, Port1 ],
27 [], [
28 // P0 only
29 // InstrItinData<class, [InstrStage<N, [P0]>] >,
30 // P0 or P1
31 // InstrItinData<class, [InstrStage<N, [P0, P1]>] >,
32 // P0 and P1
33 // InstrItinData<class, [InstrStage<N, [P0], 0>, InstrStage<N, [P1]>] >,
34 //
35 // Default is 1 cycle, port0 or port1
36 InstrItinData<IIC_ALU_MEM, [InstrStage<1, [Port0]>] >,
37 InstrItinData<IIC_ALU_NONMEM, [InstrStage<1, [Port0, Port1]>] >,
38 InstrItinData<IIC_LEA, [InstrStage<1, [Port1]>] >,
39 InstrItinData<IIC_LEA_16, [InstrStage<2, [Port0, Port1]>] >,
40 // mul
41 InstrItinData<IIC_MUL8, [InstrStage<7, [Port0, Port1]>] >,
42 InstrItinData<IIC_MUL16_MEM, [InstrStage<8, [Port0, Port1]>] >,
43 InstrItinData<IIC_MUL16_REG, [InstrStage<7, [Port0, Port1]>] >,
44 InstrItinData<IIC_MUL32_MEM, [InstrStage<7, [Port0, Port1]>] >,
45 InstrItinData<IIC_MUL32_REG, [InstrStage<6, [Port0, Port1]>] >,
46 InstrItinData<IIC_MUL64, [InstrStage<12, [Port0, Port1]>] >,
47 // imul by al, ax, eax, rax
48 InstrItinData<IIC_IMUL8, [InstrStage<7, [Port0, Port1]>] >,
49 InstrItinData<IIC_IMUL16_MEM, [InstrStage<8, [Port0, Port1]>] >,
50 InstrItinData<IIC_IMUL16_REG, [InstrStage<7, [Port0, Port1]>] >,
51 InstrItinData<IIC_IMUL32_MEM, [InstrStage<7, [Port0, Port1]>] >,
52 InstrItinData<IIC_IMUL32_REG, [InstrStage<6, [Port0, Port1]>] >,
53 InstrItinData<IIC_IMUL64, [InstrStage<12, [Port0, Port1]>] >,
54 // imul reg by reg|mem
55 InstrItinData<IIC_IMUL16_RM, [InstrStage<7, [Port0, Port1]>] >,
56 InstrItinData<IIC_IMUL16_RR, [InstrStage<6, [Port0, Port1]>] >,
57 InstrItinData<IIC_IMUL32_RM, [InstrStage<5, [Port0]>] >,
58 InstrItinData<IIC_IMUL32_RR, [InstrStage<5, [Port0]>] >,
59 InstrItinData<IIC_IMUL64_RM, [InstrStage<12, [Port0, Port1]>] >,
60 InstrItinData<IIC_IMUL64_RR, [InstrStage<12, [Port0, Port1]>] >,
61 // imul reg = reg/mem * imm
62 InstrItinData<IIC_IMUL16_RRI, [InstrStage<6, [Port0, Port1]>] >,
63 InstrItinData<IIC_IMUL32_RRI, [InstrStage<5, [Port0]>] >,
64 InstrItinData<IIC_IMUL64_RRI, [InstrStage<14, [Port0, Port1]>] >,
65 InstrItinData<IIC_IMUL16_RMI, [InstrStage<7, [Port0, Port1]>] >,
66 InstrItinData<IIC_IMUL32_RMI, [InstrStage<5, [Port0]>] >,
67 InstrItinData<IIC_IMUL64_RMI, [InstrStage<14, [Port0, Port1]>] >,
68 // idiv
69 InstrItinData<IIC_IDIV8, [InstrStage<62, [Port0, Port1]>] >,
70 InstrItinData<IIC_IDIV16, [InstrStage<62, [Port0, Port1]>] >,
71 InstrItinData<IIC_IDIV32, [InstrStage<62, [Port0, Port1]>] >,
72 InstrItinData<IIC_IDIV64, [InstrStage<130, [Port0, Port1]>] >,
73 // div
74 InstrItinData<IIC_DIV8_REG, [InstrStage<50, [Port0, Port1]>] >,
75 InstrItinData<IIC_DIV8_MEM, [InstrStage<68, [Port0, Port1]>] >,
76 InstrItinData<IIC_DIV16, [InstrStage<50, [Port0, Port1]>] >,
77 InstrItinData<IIC_DIV32, [InstrStage<50, [Port0, Port1]>] >,
78 InstrItinData<IIC_DIV64, [InstrStage<130, [Port0, Port1]>] >,
79 // neg/not/inc/dec
80 InstrItinData<IIC_UNARY_REG, [InstrStage<1, [Port0, Port1]>] >,
81 InstrItinData<IIC_UNARY_MEM, [InstrStage<1, [Port0]>] >,
82 // add/sub/and/or/xor/cmp/test
83 InstrItinData<IIC_BIN_NONMEM, [InstrStage<1, [Port0, Port1]>] >,
84 InstrItinData<IIC_BIN_MEM, [InstrStage<1, [Port0]>] >,
85 // adc/sbc
86 InstrItinData<IIC_BIN_CARRY_NONMEM, [InstrStage<1, [Port0, Port1]>] >,
87 InstrItinData<IIC_BIN_CARRY_MEM, [InstrStage<1, [Port0]>] >,
88 // shift/rotate
89 InstrItinData<IIC_SR, [InstrStage<1, [Port0]>] >,
90 // shift double
91 InstrItinData<IIC_SHD16_REG_IM, [InstrStage<6, [Port0, Port1]>] >,
92 InstrItinData<IIC_SHD16_REG_CL, [InstrStage<6, [Port0, Port1]>] >,
93 InstrItinData<IIC_SHD16_MEM_IM, [InstrStage<6, [Port0, Port1]>] >,
94 InstrItinData<IIC_SHD16_MEM_CL, [InstrStage<6, [Port0, Port1]>] >,
95 InstrItinData<IIC_SHD32_REG_IM, [InstrStage<2, [Port0, Port1]>] >,
96 InstrItinData<IIC_SHD32_REG_CL, [InstrStage<2, [Port0, Port1]>] >,
97 InstrItinData<IIC_SHD32_MEM_IM, [InstrStage<4, [Port0, Port1]>] >,
98 InstrItinData<IIC_SHD32_MEM_CL, [InstrStage<4, [Port0, Port1]>] >,
99 InstrItinData<IIC_SHD64_REG_IM, [InstrStage<9, [Port0, Port1]>] >,
100 InstrItinData<IIC_SHD64_REG_CL, [InstrStage<8, [Port0, Port1]>] >,
101 InstrItinData<IIC_SHD64_MEM_IM, [InstrStage<9, [Port0, Port1]>] >,
102 InstrItinData<IIC_SHD64_MEM_CL, [InstrStage<9, [Port0, Port1]>] >,
103 // cmov
104 InstrItinData<IIC_CMOV16_RM, [InstrStage<1, [Port0]>] >,
105 InstrItinData<IIC_CMOV16_RR, [InstrStage<1, [Port0, Port1]>] >,
106 InstrItinData<IIC_CMOV32_RM, [InstrStage<1, [Port0]>] >,
107 InstrItinData<IIC_CMOV32_RR, [InstrStage<1, [Port0, Port1]>] >,
108 InstrItinData<IIC_CMOV64_RM, [InstrStage<1, [Port0]>] >,
109 InstrItinData<IIC_CMOV64_RR, [InstrStage<1, [Port0, Port1]>] >,
110 // set
111 InstrItinData<IIC_SET_M, [InstrStage<2, [Port0, Port1]>] >,
112 InstrItinData<IIC_SET_R, [InstrStage<1, [Port0, Port1]>] >,
113 // jcc
114 InstrItinData<IIC_Jcc, [InstrStage<1, [Port1]>] >,
115 // jcxz/jecxz/jrcxz
116 InstrItinData<IIC_JCXZ, [InstrStage<4, [Port0, Port1]>] >,
117 // jmp rel
118 InstrItinData<IIC_JMP_REL, [InstrStage<1, [Port1]>] >,
119 // jmp indirect
120 InstrItinData<IIC_JMP_REG, [InstrStage<1, [Port1]>] >,
121 InstrItinData<IIC_JMP_MEM, [InstrStage<2, [Port0, Port1]>] >,
122 // jmp far
123 InstrItinData<IIC_JMP_FAR_MEM, [InstrStage<32, [Port0, Port1]>] >,
124 InstrItinData<IIC_JMP_FAR_PTR, [InstrStage<31, [Port0, Port1]>] >,
125 // loop/loope/loopne
126 InstrItinData<IIC_LOOP, [InstrStage<18, [Port0, Port1]>] >,
127 InstrItinData<IIC_LOOPE, [InstrStage<8, [Port0, Port1]>] >,
128 InstrItinData<IIC_LOOPNE, [InstrStage<17, [Port0, Port1]>] >,
129 // call - all but reg/imm
130 InstrItinData<IIC_CALL_RI, [InstrStage<1, [Port0], 0>,
131 InstrStage<1, [Port1]>] >,
132 InstrItinData<IIC_CALL_MEM, [InstrStage<15, [Port0, Port1]>] >,
133 InstrItinData<IIC_CALL_FAR_MEM, [InstrStage<40, [Port0, Port1]>] >,
134 InstrItinData<IIC_CALL_FAR_PTR, [InstrStage<39, [Port0, Port1]>] >,
135 //ret
136 InstrItinData<IIC_RET, [InstrStage<79, [Port0, Port1]>] >,
137 InstrItinData<IIC_RET_IMM, [InstrStage<1, [Port0], 0>, InstrStage<1, [Port1]>] >,
138 //sign extension movs
139 InstrItinData<IIC_MOVSX,[InstrStage<1, [Port0] >] >,
140 InstrItinData<IIC_MOVSX_R16_R8, [InstrStage<2, [Port0, Port1]>] >,
141 InstrItinData<IIC_MOVSX_R16_M8, [InstrStage<3, [Port0, Port1]>] >,
142 InstrItinData<IIC_MOVSX_R16_R16, [InstrStage<1, [Port0, Port1]>] >,
143 InstrItinData<IIC_MOVSX_R32_R32, [InstrStage<1, [Port0, Port1]>] >,
144 //zero extension movs
145 InstrItinData<IIC_MOVZX,[InstrStage<1, [Port0]>] >,
146 InstrItinData<IIC_MOVZX_R16_R8, [InstrStage<2, [Port0, Port1]>] >,
147 InstrItinData<IIC_MOVZX_R16_M8, [InstrStage<3, [Port0, Port1]>] >,
148
149 InstrItinData<IIC_REP_MOVS, [InstrStage<75, [Port0, Port1]>] >,
150 InstrItinData<IIC_REP_STOS, [InstrStage<74, [Port0, Port1]>] >,
151
152 // SSE binary operations
153 // arithmetic fp scalar
154 InstrItinData<IIC_SSE_ALU_F32S_RR, [InstrStage<5, [Port1]>] >,
155 InstrItinData<IIC_SSE_ALU_F32S_RM, [InstrStage<5, [Port0], 0>,
156 InstrStage<5, [Port1]>] >,
157 InstrItinData<IIC_SSE_ALU_F64S_RR, [InstrStage<5, [Port1]>] >,
158 InstrItinData<IIC_SSE_ALU_F64S_RM, [InstrStage<5, [Port0], 0>,
159 InstrStage<5, [Port1]>] >,
160 InstrItinData<IIC_SSE_MUL_F32S_RR, [InstrStage<4, [Port0]>] >,
161 InstrItinData<IIC_SSE_MUL_F32S_RM, [InstrStage<4, [Port0]>] >,
162 InstrItinData<IIC_SSE_MUL_F64S_RR, [InstrStage<5, [Port0]>] >,
163 InstrItinData<IIC_SSE_MUL_F64S_RM, [InstrStage<5, [Port0]>] >,
164 InstrItinData<IIC_SSE_DIV_F32S_RR, [InstrStage<34, [Port0, Port1]>] >,
165 InstrItinData<IIC_SSE_DIV_F32S_RM, [InstrStage<34, [Port0, Port1]>] >,
166 InstrItinData<IIC_SSE_DIV_F64S_RR, [InstrStage<62, [Port0, Port1]>] >,
167 InstrItinData<IIC_SSE_DIV_F64S_RM, [InstrStage<62, [Port0, Port1]>] >,
168
169 InstrItinData<IIC_SSE_COMIS_RR, [InstrStage<9, [Port0, Port1]>] >,
170 InstrItinData<IIC_SSE_COMIS_RM, [InstrStage<10, [Port0, Port1]>] >,
171
172 InstrItinData<IIC_SSE_HADDSUB_RR, [InstrStage<8, [Port0, Port1]>] >,
173 InstrItinData<IIC_SSE_HADDSUB_RM, [InstrStage<9, [Port0, Port1]>] >,
174
175 // arithmetic fp parallel
176 InstrItinData<IIC_SSE_ALU_F32P_RR, [InstrStage<5, [Port1]>] >,
177 InstrItinData<IIC_SSE_ALU_F32P_RM, [InstrStage<5, [Port0], 0>,
178 InstrStage<5, [Port1]>] >,
179 InstrItinData<IIC_SSE_ALU_F64P_RR, [InstrStage<6, [Port0, Port1]>] >,
180 InstrItinData<IIC_SSE_ALU_F64P_RM, [InstrStage<7, [Port0, Port1]>] >,
181 InstrItinData<IIC_SSE_MUL_F32P_RR, [InstrStage<5, [Port0]>] >,
182 InstrItinData<IIC_SSE_MUL_F32P_RM, [InstrStage<5, [Port0]>] >,
183 InstrItinData<IIC_SSE_MUL_F64P_RR, [InstrStage<9, [Port0, Port1]>] >,
184 InstrItinData<IIC_SSE_MUL_F64P_RM, [InstrStage<10, [Port0, Port1]>] >,
185 InstrItinData<IIC_SSE_DIV_F32P_RR, [InstrStage<70, [Port0, Port1]>] >,
186 InstrItinData<IIC_SSE_DIV_F32P_RM, [InstrStage<70, [Port0, Port1]>] >,
187 InstrItinData<IIC_SSE_DIV_F64P_RR, [InstrStage<125, [Port0, Port1]>] >,
188 InstrItinData<IIC_SSE_DIV_F64P_RM, [InstrStage<125, [Port0, Port1]>] >,
189
190 // bitwise parallel
191 InstrItinData<IIC_SSE_BIT_P_RR, [InstrStage<1, [Port0, Port1]>] >,
192 InstrItinData<IIC_SSE_BIT_P_RM, [InstrStage<1, [Port0]>] >,
193
194 // arithmetic int parallel
195 InstrItinData<IIC_SSE_INTALU_P_RR, [InstrStage<1, [Port0, Port1]>] >,
196 InstrItinData<IIC_SSE_INTALU_P_RM, [InstrStage<1, [Port0]>] >,
197 InstrItinData<IIC_SSE_INTALUQ_P_RR, [InstrStage<2, [Port0, Port1]>] >,
198 InstrItinData<IIC_SSE_INTALUQ_P_RM, [InstrStage<3, [Port0, Port1]>] >,
199
200 // multiply int parallel
201 InstrItinData<IIC_SSE_INTMUL_P_RR, [InstrStage<5, [Port0]>] >,
202 InstrItinData<IIC_SSE_INTMUL_P_RM, [InstrStage<5, [Port0]>] >,
203
204 // shift parallel
205 InstrItinData<IIC_SSE_INTSH_P_RR, [InstrStage<2, [Port0, Port1]>] >,
206 InstrItinData<IIC_SSE_INTSH_P_RM, [InstrStage<3, [Port0, Port1]>] >,
207 InstrItinData<IIC_SSE_INTSH_P_RI, [InstrStage<1, [Port0, Port1]>] >,
208
209 InstrItinData<IIC_SSE_INTSHDQ_P_RI, [InstrStage<1, [Port0, Port1]>] >,
210
211 InstrItinData<IIC_SSE_SHUFP, [InstrStage<1, [Port0]>] >,
212 InstrItinData<IIC_SSE_PSHUF_RI, [InstrStage<1, [Port0]>] >,
213 InstrItinData<IIC_SSE_PSHUF_MI, [InstrStage<1, [Port0]>] >,
214
215 InstrItinData<IIC_SSE_PACK, [InstrStage<1, [Port0]>] >,
216 InstrItinData<IIC_SSE_UNPCK, [InstrStage<1, [Port0]>] >,
217
218 InstrItinData<IIC_SSE_SQRTPS_RR, [InstrStage<70, [Port0, Port1]>] >,
219 InstrItinData<IIC_SSE_SQRTPS_RM, [InstrStage<70, [Port0, Port1]>] >,
220 InstrItinData<IIC_SSE_SQRTSS_RR, [InstrStage<34, [Port0, Port1]>] >,
221 InstrItinData<IIC_SSE_SQRTSS_RM, [InstrStage<34, [Port0, Port1]>] >,
222
223 InstrItinData<IIC_SSE_SQRTPD_RR, [InstrStage<125, [Port0, Port1]>] >,
224 InstrItinData<IIC_SSE_SQRTPD_RM, [InstrStage<125, [Port0, Port1]>] >,
225 InstrItinData<IIC_SSE_SQRTSD_RR, [InstrStage<62, [Port0, Port1]>] >,
226 InstrItinData<IIC_SSE_SQRTSD_RM, [InstrStage<62, [Port0, Port1]>] >,
227
228 InstrItinData<IIC_SSE_RSQRTPS_RR, [InstrStage<9, [Port0, Port1]>] >,
229 InstrItinData<IIC_SSE_RSQRTPS_RM, [InstrStage<10, [Port0, Port1]>] >,
230 InstrItinData<IIC_SSE_RSQRTSS_RR, [InstrStage<4, [Port0]>] >,
231 InstrItinData<IIC_SSE_RSQRTSS_RM, [InstrStage<4, [Port0]>] >,
232
233 InstrItinData<IIC_SSE_RCPP_RR, [InstrStage<9, [Port0, Port1]>] >,
234 InstrItinData<IIC_SSE_RCPP_RM, [InstrStage<10, [Port0, Port1]>] >,
235 InstrItinData<IIC_SSE_RCPS_RR, [InstrStage<4, [Port0]>] >,
236 InstrItinData<IIC_SSE_RCPS_RM, [InstrStage<4, [Port0]>] >,
237
238 InstrItinData<IIC_SSE_MOVMSK, [InstrStage<3, [Port0]>] >,
239 InstrItinData<IIC_SSE_MASKMOV, [InstrStage<2, [Port0, Port1]>] >,
240
241 InstrItinData<IIC_SSE_PEXTRW, [InstrStage<4, [Port0, Port1]>] >,
242 InstrItinData<IIC_SSE_PINSRW, [InstrStage<1, [Port0]>] >,
243
244 InstrItinData<IIC_SSE_PABS_RR, [InstrStage<1, [Port0, Port1]>] >,
245 InstrItinData<IIC_SSE_PABS_RM, [InstrStage<1, [Port0]>] >,
246
247 InstrItinData<IIC_SSE_MOV_S_RR, [InstrStage<1, [Port0, Port1]>] >,
248 InstrItinData<IIC_SSE_MOV_S_RM, [InstrStage<1, [Port0]>] >,
249 InstrItinData<IIC_SSE_MOV_S_MR, [InstrStage<1, [Port0]>] >,
250
251 InstrItinData<IIC_SSE_MOVA_P_RR, [InstrStage<1, [Port0, Port1]>] >,
252 InstrItinData<IIC_SSE_MOVA_P_RM, [InstrStage<1, [Port0]>] >,
253 InstrItinData<IIC_SSE_MOVA_P_MR, [InstrStage<1, [Port0]>] >,
254
255 InstrItinData<IIC_SSE_MOVU_P_RR, [InstrStage<1, [Port0, Port1]>] >,
256 InstrItinData<IIC_SSE_MOVU_P_RM, [InstrStage<3, [Port0, Port1]>] >,
257 InstrItinData<IIC_SSE_MOVU_P_MR, [InstrStage<2, [Port0, Port1]>] >,
258
259 InstrItinData<IIC_SSE_MOV_LH, [InstrStage<1, [Port0]>] >,
260
261 InstrItinData<IIC_SSE_LDDQU, [InstrStage<3, [Port0, Port1]>] >,
262
263 InstrItinData<IIC_SSE_MOVDQ, [InstrStage<1, [Port0]>] >,
264 InstrItinData<IIC_SSE_MOVD_ToGP, [InstrStage<3, [Port0]>] >,
265 InstrItinData<IIC_SSE_MOVQ_RR, [InstrStage<1, [Port0, Port1]>] >,
266
267 InstrItinData<IIC_SSE_MOVNT, [InstrStage<1, [Port0]>] >,
268
269 InstrItinData<IIC_SSE_PREFETCH, [InstrStage<1, [Port0]>] >,
270 InstrItinData<IIC_SSE_PAUSE, [InstrStage<17, [Port0, Port1]>] >,
271 InstrItinData<IIC_SSE_LFENCE, [InstrStage<1, [Port0, Port1]>] >,
272 InstrItinData<IIC_SSE_MFENCE, [InstrStage<1, [Port0]>] >,
273 InstrItinData<IIC_SSE_SFENCE, [InstrStage<1, [Port0]>] >,
274 InstrItinData<IIC_SSE_LDMXCSR, [InstrStage<5, [Port0, Port1]>] >,
275 InstrItinData<IIC_SSE_STMXCSR, [InstrStage<15, [Port0, Port1]>] >,
276
277 InstrItinData<IIC_SSE_PHADDSUBD_RR, [InstrStage<3, [Port0, Port1]>] >,
278 InstrItinData<IIC_SSE_PHADDSUBD_RM, [InstrStage<4, [Port0, Port1]>] >,
279 InstrItinData<IIC_SSE_PHADDSUBSW_RR, [InstrStage<7, [Port0, Port1]>] >,
280 InstrItinData<IIC_SSE_PHADDSUBSW_RM, [InstrStage<8, [Port0, Port1]>] >,
281 InstrItinData<IIC_SSE_PHADDSUBW_RR, [InstrStage<7, [Port0, Port1]>] >,
282 InstrItinData<IIC_SSE_PHADDSUBW_RM, [InstrStage<8, [Port0, Port1]>] >,
283 InstrItinData<IIC_SSE_PSHUFB_RR, [InstrStage<4, [Port0, Port1]>] >,
284 InstrItinData<IIC_SSE_PSHUFB_RM, [InstrStage<5, [Port0, Port1]>] >,
285 InstrItinData<IIC_SSE_PSIGN_RR, [InstrStage<1, [Port0, Port1]>] >,
286 InstrItinData<IIC_SSE_PSIGN_RM, [InstrStage<1, [Port0]>] >,
287
288 InstrItinData<IIC_SSE_PMADD, [InstrStage<5, [Port0]>] >,
289 InstrItinData<IIC_SSE_PMULHRSW, [InstrStage<5, [Port0]>] >,
290 InstrItinData<IIC_SSE_PALIGNRR, [InstrStage<1, [Port0]>] >,
291 InstrItinData<IIC_SSE_PALIGNRM, [InstrStage<1, [Port0]>] >,
292 InstrItinData<IIC_SSE_MWAIT, [InstrStage<46, [Port0, Port1]>] >,
293 InstrItinData<IIC_SSE_MONITOR, [InstrStage<45, [Port0, Port1]>] >,
294
295 // conversions
296 // to/from PD ...
297 InstrItinData<IIC_SSE_CVT_PD_RR, [InstrStage<7, [Port0, Port1]>] >,
298 InstrItinData<IIC_SSE_CVT_PD_RM, [InstrStage<8, [Port0, Port1]>] >,
299 // to/from PS except to/from PD and PS2PI
300 InstrItinData<IIC_SSE_CVT_PS_RR, [InstrStage<6, [Port0, Port1]>] >,
301 InstrItinData<IIC_SSE_CVT_PS_RM, [InstrStage<7, [Port0, Port1]>] >,
302 InstrItinData<IIC_SSE_CVT_Scalar_RR, [InstrStage<6, [Port0, Port1]>] >,
303 InstrItinData<IIC_SSE_CVT_Scalar_RM, [InstrStage<7, [Port0, Port1]>] >,
304 InstrItinData<IIC_SSE_CVT_SS2SI32_RR, [InstrStage<8, [Port0, Port1]>] >,
305 InstrItinData<IIC_SSE_CVT_SS2SI32_RM, [InstrStage<9, [Port0, Port1]>] >,
306 InstrItinData<IIC_SSE_CVT_SS2SI64_RR, [InstrStage<9, [Port0, Port1]>] >,
307 InstrItinData<IIC_SSE_CVT_SS2SI64_RM, [InstrStage<10, [Port0, Port1]>] >,
308 InstrItinData<IIC_SSE_CVT_SD2SI_RR, [InstrStage<8, [Port0, Port1]>] >,
309 InstrItinData<IIC_SSE_CVT_SD2SI_RM, [InstrStage<9, [Port0, Port1]>] >,
310
311 // MMX MOVs
312 InstrItinData<IIC_MMX_MOV_MM_RM, [InstrStage<1, [Port0]>] >,
313 InstrItinData<IIC_MMX_MOV_REG_MM, [InstrStage<3, [Port0]>] >,
314 InstrItinData<IIC_MMX_MOVQ_RM, [InstrStage<1, [Port0]>] >,
315 InstrItinData<IIC_MMX_MOVQ_RR, [InstrStage<1, [Port0, Port1]>] >,
316 // other MMX
317 InstrItinData<IIC_MMX_ALU_RM, [InstrStage<1, [Port0]>] >,
318 InstrItinData<IIC_MMX_ALU_RR, [InstrStage<1, [Port0, Port1]>] >,
319 InstrItinData<IIC_MMX_ALUQ_RM, [InstrStage<3, [Port0, Port1]>] >,
320 InstrItinData<IIC_MMX_ALUQ_RR, [InstrStage<2, [Port0, Port1]>] >,
321 InstrItinData<IIC_MMX_PHADDSUBW_RM, [InstrStage<6, [Port0, Port1]>] >,
322 InstrItinData<IIC_MMX_PHADDSUBW_RR, [InstrStage<5, [Port0, Port1]>] >,
323 InstrItinData<IIC_MMX_PHADDSUBD_RM, [InstrStage<4, [Port0, Port1]>] >,
324 InstrItinData<IIC_MMX_PHADDSUBD_RR, [InstrStage<3, [Port0, Port1]>] >,
325 InstrItinData<IIC_MMX_PMUL, [InstrStage<4, [Port0]>] >,
326 InstrItinData<IIC_MMX_MISC_FUNC_MEM, [InstrStage<1, [Port0]>] >,
327 InstrItinData<IIC_MMX_MISC_FUNC_REG, [InstrStage<1, [Port0, Port1]>] >,
328 InstrItinData<IIC_MMX_PSADBW, [InstrStage<4, [Port0, Port1]>] >,
329 InstrItinData<IIC_MMX_SHIFT_RI, [InstrStage<1, [Port0, Port1]>] >,
330 InstrItinData<IIC_MMX_SHIFT_RM, [InstrStage<3, [Port0, Port1]>] >,
331 InstrItinData<IIC_MMX_SHIFT_RR, [InstrStage<2, [Port0, Port1]>] >,
332 InstrItinData<IIC_MMX_UNPCK_H_RM, [InstrStage<1, [Port0]>] >,
333 InstrItinData<IIC_MMX_UNPCK_H_RR, [InstrStage<1, [Port0, Port1]>] >,
334 InstrItinData<IIC_MMX_UNPCK_L, [InstrStage<1, [Port0]>] >,
335 InstrItinData<IIC_MMX_PCK_RM, [InstrStage<1, [Port0]>] >,
336 InstrItinData<IIC_MMX_PCK_RR, [InstrStage<1, [Port0, Port1]>] >,
337 InstrItinData<IIC_MMX_PSHUF, [InstrStage<1, [Port0]>] >,
338 InstrItinData<IIC_MMX_PEXTR, [InstrStage<4, [Port0, Port1]>] >,
339 InstrItinData<IIC_MMX_PINSRW, [InstrStage<1, [Port0]>] >,
340 InstrItinData<IIC_MMX_MASKMOV, [InstrStage<1, [Port0]>] >,
341 InstrItinData<IIC_MMX_MOVMSK, [InstrStage<3, [Port0]>] >,
342 // conversions
343 // from/to PD
344 InstrItinData<IIC_MMX_CVT_PD_RR, [InstrStage<7, [Port0, Port1]>] >,
345 InstrItinData<IIC_MMX_CVT_PD_RM, [InstrStage<8, [Port0, Port1]>] >,
346 // from/to PI
347 InstrItinData<IIC_MMX_CVT_PS_RR, [InstrStage<5, [Port1]>] >,
348 InstrItinData<IIC_MMX_CVT_PS_RM, [InstrStage<5, [Port0], 0>,
349 InstrStage<5, [Port1]>]>,
350
351 InstrItinData<IIC_CMPX_LOCK, [InstrStage<14, [Port0, Port1]>] >,
352 InstrItinData<IIC_CMPX_LOCK_8, [InstrStage<6, [Port0, Port1]>] >,
353 InstrItinData<IIC_CMPX_LOCK_8B, [InstrStage<18, [Port0, Port1]>] >,
354 InstrItinData<IIC_CMPX_LOCK_16B, [InstrStage<22, [Port0, Port1]>] >,
355
356 InstrItinData<IIC_XADD_LOCK_MEM, [InstrStage<2, [Port0, Port1]>] >,
357 InstrItinData<IIC_XADD_LOCK_MEM, [InstrStage<3, [Port0, Port1]>] >,
358
359 InstrItinData<IIC_FILD, [InstrStage<5, [Port0], 0>, InstrStage<5, [Port1]>] >,
360 InstrItinData<IIC_FLD, [InstrStage<1, [Port0]>] >,
361 InstrItinData<IIC_FLD80, [InstrStage<4, [Port0, Port1]>] >,
362
363 InstrItinData<IIC_FST, [InstrStage<2, [Port0, Port1]>] >,
364 InstrItinData<IIC_FST80, [InstrStage<5, [Port0, Port1]>] >,
365 InstrItinData<IIC_FIST, [InstrStage<6, [Port0, Port1]>] >,
366
367 InstrItinData<IIC_FCMOV, [InstrStage<9, [Port0, Port1]>] >,
368 InstrItinData<IIC_FLDZ, [InstrStage<1, [Port0, Port1]>] >,
369 InstrItinData<IIC_FUCOM, [InstrStage<1, [Port1]>] >,
370 InstrItinData<IIC_FUCOMI, [InstrStage<9, [Port0, Port1]>] >,
371 InstrItinData<IIC_FCOMI, [InstrStage<9, [Port0, Port1]>] >,
372 InstrItinData<IIC_FNSTSW, [InstrStage<10, [Port0, Port1]>] >,
373 InstrItinData<IIC_FNSTCW, [InstrStage<8, [Port0, Port1]>] >,
374 InstrItinData<IIC_FLDCW, [InstrStage<5, [Port0, Port1]>] >,
375 InstrItinData<IIC_FNINIT, [InstrStage<63, [Port0, Port1]>] >,
376 InstrItinData<IIC_FFREE, [InstrStage<1, [Port0, Port1]>] >,
377 InstrItinData<IIC_FNCLEX, [InstrStage<25, [Port0, Port1]>] >,
378 InstrItinData<IIC_WAIT, [InstrStage<1, [Port0, Port1]>] >,
379 InstrItinData<IIC_FXAM, [InstrStage<1, [Port0]>] >,
380 InstrItinData<IIC_FNOP, [InstrStage<1, [Port0, Port1]>] >,
381 InstrItinData<IIC_FLDL, [InstrStage<10, [Port0, Port1]>] >,
382 InstrItinData<IIC_F2XM1, [InstrStage<99, [Port0, Port1]>] >,
383 InstrItinData<IIC_FYL2X, [InstrStage<146, [Port0, Port1]>] >,
384 InstrItinData<IIC_FPTAN, [InstrStage<168, [Port0, Port1]>] >,
385 InstrItinData<IIC_FPATAN, [InstrStage<183, [Port0, Port1]>] >,
386 InstrItinData<IIC_FXTRACT, [InstrStage<25, [Port0, Port1]>] >,
387 InstrItinData<IIC_FPREM1, [InstrStage<71, [Port0, Port1]>] >,
388 InstrItinData<IIC_FPSTP, [InstrStage<1, [Port0, Port1]>] >,
389 InstrItinData<IIC_FPREM, [InstrStage<55, [Port0, Port1]>] >,
390 InstrItinData<IIC_FYL2XP1, [InstrStage<147, [Port0, Port1]>] >,
391 InstrItinData<IIC_FSINCOS, [InstrStage<174, [Port0, Port1]>] >,
392 InstrItinData<IIC_FRNDINT, [InstrStage<46, [Port0, Port1]>] >,
393 InstrItinData<IIC_FSCALE, [InstrStage<77, [Port0, Port1]>] >,
394 InstrItinData<IIC_FCOMPP, [InstrStage<1, [Port1]>] >,
395 InstrItinData<IIC_FXSAVE, [InstrStage<140, [Port0, Port1]>] >,
396 InstrItinData<IIC_FXRSTOR, [InstrStage<141, [Port0, Port1]>] >,
397 InstrItinData<IIC_FXCH, [InstrStage<1, [Port0], 0>, InstrStage<1, [Port1]>] >,
398 InstrItinData<IIC_FSIGN, [InstrStage<1, [Port1]>] >,
399 InstrItinData<IIC_FSQRT, [InstrStage<71, [Port0, Port1]>] >,
400
401 // System instructions
402 InstrItinData<IIC_CPUID, [InstrStage<121, [Port0, Port1]>] >,
403 InstrItinData<IIC_INT, [InstrStage<127, [Port0, Port1]>] >,
404 InstrItinData<IIC_INT3, [InstrStage<130, [Port0, Port1]>] >,
405 InstrItinData<IIC_INVD, [InstrStage<1003, [Port0, Port1]>] >,
406 InstrItinData<IIC_INVLPG, [InstrStage<71, [Port0, Port1]>] >,
407 InstrItinData<IIC_IRET, [InstrStage<109, [Port0, Port1]>] >,
408 InstrItinData<IIC_HLT, [InstrStage<121, [Port0, Port1]>] >,
409 InstrItinData<IIC_LXS, [InstrStage<10, [Port0, Port1]>] >,
410 InstrItinData<IIC_LTR, [InstrStage<83, [Port0, Port1]>] >,
411 InstrItinData<IIC_RDTSC, [InstrStage<30, [Port0, Port1]>] >,
412 InstrItinData<IIC_RDTSCP, [InstrStage<30, [Port0, Port1]>] >,
413 InstrItinData<IIC_RSM, [InstrStage<741, [Port0, Port1]>] >,
414 InstrItinData<IIC_SIDT, [InstrStage<4, [Port0, Port1]>] >,
415 InstrItinData<IIC_SGDT, [InstrStage<4, [Port0, Port1]>] >,
416 InstrItinData<IIC_SLDT, [InstrStage<3, [Port0, Port1]>] >,
417 InstrItinData<IIC_STR, [InstrStage<3, [Port0, Port1]>] >,
418 InstrItinData<IIC_SWAPGS, [InstrStage<22, [Port0, Port1]>] >,
419 InstrItinData<IIC_SYSCALL, [InstrStage<96, [Port0, Port1]>] >,
420 InstrItinData<IIC_SYS_ENTER_EXIT, [InstrStage<88, [Port0, Port1]>] >,
421
422 InstrItinData<IIC_IN_RR, [InstrStage<94, [Port0, Port1]>] >,
423 InstrItinData<IIC_IN_RI, [InstrStage<92, [Port0, Port1]>] >,
424 InstrItinData<IIC_OUT_RR, [InstrStage<68, [Port0, Port1]>] >,
425 InstrItinData<IIC_OUT_IR, [InstrStage<72, [Port0, Port1]>] >,
426 InstrItinData<IIC_INS, [InstrStage<59, [Port0, Port1]>] >,
427
428 InstrItinData<IIC_MOV_REG_DR, [InstrStage<88, [Port0, Port1]>] >,
429 InstrItinData<IIC_MOV_DR_REG, [InstrStage<123, [Port0, Port1]>] >,
430 // worst case for mov REG_CRx
431 InstrItinData<IIC_MOV_REG_CR, [InstrStage<12, [Port0, Port1]>] >,
432 InstrItinData<IIC_MOV_CR_REG, [InstrStage<136, [Port0, Port1]>] >,
433
434 InstrItinData<IIC_MOV_REG_SR, [InstrStage<1, [Port0]>] >,
435 InstrItinData<IIC_MOV_MEM_SR, [InstrStage<2, [Port0, Port1]>] >,
436 InstrItinData<IIC_MOV_SR_REG, [InstrStage<21, [Port0, Port1]>] >,
437 InstrItinData<IIC_MOV_SR_MEM, [InstrStage<26, [Port0, Port1]>] >,
438 // LAR
439 InstrItinData<IIC_LAR_RM, [InstrStage<50, [Port0, Port1]>] >,
440 InstrItinData<IIC_LAR_RR, [InstrStage<54, [Port0, Port1]>] >,
441 // LSL
442 InstrItinData<IIC_LSL_RM, [InstrStage<46, [Port0, Port1]>] >,
443 InstrItinData<IIC_LSL_RR, [InstrStage<49, [Port0, Port1]>] >,
444
445 InstrItinData<IIC_LGDT, [InstrStage<44, [Port0, Port1]>] >,
446 InstrItinData<IIC_LIDT, [InstrStage<44, [Port0, Port1]>] >,
447 InstrItinData<IIC_LLDT_REG, [InstrStage<60, [Port0, Port1]>] >,
448 InstrItinData<IIC_LLDT_MEM, [InstrStage<64, [Port0, Port1]>] >,
449 // push control register, segment registers
450 InstrItinData<IIC_PUSH_CS, [InstrStage<2, [Port0, Port1]>] >,
451 InstrItinData<IIC_PUSH_SR, [InstrStage<2, [Port0, Port1]>] >,
452 // pop control register, segment registers
453 InstrItinData<IIC_POP_SR, [InstrStage<29, [Port0, Port1]>] >,
454 InstrItinData<IIC_POP_SR_SS, [InstrStage<48, [Port0, Port1]>] >,
455 // VERR, VERW
456 InstrItinData<IIC_VERR, [InstrStage<41, [Port0, Port1]>] >,
457 InstrItinData<IIC_VERW_REG, [InstrStage<51, [Port0, Port1]>] >,
458 InstrItinData<IIC_VERW_MEM, [InstrStage<50, [Port0, Port1]>] >,
459 // WRMSR, RDMSR
460 InstrItinData<IIC_WRMSR, [InstrStage<202, [Port0, Port1]>] >,
461 InstrItinData<IIC_RDMSR, [InstrStage<78, [Port0, Port1]>] >,
462 InstrItinData<IIC_RDPMC, [InstrStage<46, [Port0, Port1]>] >,
463 // SMSW, LMSW
464 InstrItinData<IIC_SMSW, [InstrStage<9, [Port0, Port1]>] >,
465 InstrItinData<IIC_LMSW_REG, [InstrStage<69, [Port0, Port1]>] >,
466 InstrItinData<IIC_LMSW_MEM, [InstrStage<67, [Port0, Port1]>] >,
467
468 InstrItinData<IIC_ENTER, [InstrStage<32, [Port0, Port1]>] >,
469 InstrItinData<IIC_LEAVE, [InstrStage<2, [Port0, Port1]>] >,
470
471 InstrItinData<IIC_POP_MEM, [InstrStage<3, [Port0, Port1]>] >,
472 InstrItinData<IIC_POP_REG16, [InstrStage<2, [Port0, Port1]>] >,
473 InstrItinData<IIC_POP_REG, [InstrStage<1, [Port0], 0>,
474 InstrStage<1, [Port1]>] >,
475 InstrItinData<IIC_POP_F, [InstrStage<32, [Port0, Port1]>] >,
476 InstrItinData<IIC_POP_FD, [InstrStage<26, [Port0, Port1]>] >,
477 InstrItinData<IIC_POP_A, [InstrStage<9, [Port0, Port1]>] >,
478
479 InstrItinData<IIC_PUSH_IMM, [InstrStage<1, [Port0], 0>,
480 InstrStage<1, [Port1]>] >,
481 InstrItinData<IIC_PUSH_MEM, [InstrStage<2, [Port0, Port1]>] >,
482 InstrItinData<IIC_PUSH_REG, [InstrStage<1, [Port0], 0>,
483 InstrStage<1, [Port1]>] >,
484 InstrItinData<IIC_PUSH_F, [InstrStage<9, [Port0, Port1]>] >,
485 InstrItinData<IIC_PUSH_A, [InstrStage<8, [Port0, Port1]>] >,
486
487 InstrItinData<IIC_BSWAP, [InstrStage<1, [Port0]>] >,
488 InstrItinData<IIC_BIT_SCAN_MEM, [InstrStage<16, [Port0, Port1]>] >,
489 InstrItinData<IIC_BIT_SCAN_REG, [InstrStage<16, [Port0, Port1]>] >,
490 InstrItinData<IIC_MOVS, [InstrStage<3, [Port0, Port1]>] >,
491 InstrItinData<IIC_STOS, [InstrStage<1, [Port0, Port1]>] >,
492 InstrItinData<IIC_SCAS, [InstrStage<2, [Port0, Port1]>] >,
493 InstrItinData<IIC_CMPS, [InstrStage<3, [Port0, Port1]>] >,
494 InstrItinData<IIC_MOV, [InstrStage<1, [Port0, Port1]>] >,
495 InstrItinData<IIC_MOV_MEM, [InstrStage<1, [Port0]>] >,
496 InstrItinData<IIC_AHF, [InstrStage<1, [Port0, Port1]>] >,
497 InstrItinData<IIC_BT_MI, [InstrStage<1, [Port0, Port1]>] >,
498 InstrItinData<IIC_BT_MR, [InstrStage<9, [Port0, Port1]>] >,
499 InstrItinData<IIC_BT_RI, [InstrStage<1, [Port1]>] >,
500 InstrItinData<IIC_BT_RR, [InstrStage<1, [Port1]>] >,
501 InstrItinData<IIC_BTX_MI, [InstrStage<2, [Port0, Port1]>] >,
502 InstrItinData<IIC_BTX_MR, [InstrStage<11, [Port0, Port1]>] >,
503 InstrItinData<IIC_BTX_RI, [InstrStage<1, [Port1]>] >,
504 InstrItinData<IIC_BTX_RR, [InstrStage<1, [Port1]>] >,
505 InstrItinData<IIC_XCHG_REG, [InstrStage<2, [Port0, Port1]>] >,
506 InstrItinData<IIC_XCHG_MEM, [InstrStage<3, [Port0, Port1]>] >,
507 InstrItinData<IIC_XADD_REG, [InstrStage<2, [Port0, Port1]>] >,
508 InstrItinData<IIC_XADD_MEM, [InstrStage<3, [Port0, Port1]>] >,
509 InstrItinData<IIC_CMPXCHG_MEM, [InstrStage<14, [Port0, Port1]>] >,
510 InstrItinData<IIC_CMPXCHG_REG, [InstrStage<15, [Port0, Port1]>] >,
511 InstrItinData<IIC_CMPXCHG_MEM8, [InstrStage<6, [Port0, Port1]>] >,
512 InstrItinData<IIC_CMPXCHG_REG8, [InstrStage<9, [Port0, Port1]>] >,
513 InstrItinData<IIC_CMPXCHG_8B, [InstrStage<18, [Port0, Port1]>] >,
514 InstrItinData<IIC_CMPXCHG_16B, [InstrStage<22, [Port0, Port1]>] >,
515 InstrItinData<IIC_LODS, [InstrStage<2, [Port0, Port1]>] >,
516 InstrItinData<IIC_OUTS, [InstrStage<74, [Port0, Port1]>] >,
517 InstrItinData<IIC_CLC, [InstrStage<1, [Port0, Port1]>] >,
518 InstrItinData<IIC_CLD, [InstrStage<3, [Port0, Port1]>] >,
519 InstrItinData<IIC_CLI, [InstrStage<14, [Port0, Port1]>] >,
520 InstrItinData<IIC_CMC, [InstrStage<1, [Port0, Port1]>] >,
521 InstrItinData<IIC_CLTS, [InstrStage<33, [Port0, Port1]>] >,
522 InstrItinData<IIC_STC, [InstrStage<1, [Port0, Port1]>] >,
523 InstrItinData<IIC_STI, [InstrStage<17, [Port0, Port1]>] >,
524 InstrItinData<IIC_STD, [InstrStage<21, [Port0, Port1]>] >,
525 InstrItinData<IIC_XLAT, [InstrStage<6, [Port0, Port1]>] >,
526 InstrItinData<IIC_AAA, [InstrStage<13, [Port0, Port1]>] >,
527 InstrItinData<IIC_AAD, [InstrStage<7, [Port0, Port1]>] >,
528 InstrItinData<IIC_AAM, [InstrStage<21, [Port0, Port1]>] >,
529 InstrItinData<IIC_AAS, [InstrStage<13, [Port0, Port1]>] >,
530 InstrItinData<IIC_DAA, [InstrStage<18, [Port0, Port1]>] >,
531 InstrItinData<IIC_DAS, [InstrStage<20, [Port0, Port1]>] >,
532 InstrItinData<IIC_BOUND, [InstrStage<11, [Port0, Port1]>] >,
533 InstrItinData<IIC_ARPL_REG, [InstrStage<24, [Port0, Port1]>] >,
534 InstrItinData<IIC_ARPL_MEM, [InstrStage<23, [Port0, Port1]>] >,
535 InstrItinData<IIC_MOVBE, [InstrStage<1, [Port0]>] >,
536 InstrItinData<IIC_CBW, [InstrStage<4, [Port0, Port1]>] >,
537 InstrItinData<IIC_MMX_EMMS, [InstrStage<5, [Port0, Port1]>] >,
538
539 InstrItinData<IIC_NOP, [InstrStage<1, [Port0, Port1]>] >
540 ]>;
541 17
542 // Atom machine model. 18 // Atom machine model.
543 def AtomModel : SchedMachineModel { 19 def AtomModel : SchedMachineModel {
544 let IssueWidth = 2; // Allows 2 instructions per scheduling group. 20 let IssueWidth = 2; // Allows 2 instructions per scheduling group.
545 let MicroOpBufferSize = 0; // In-order execution, always hide latency. 21 let MicroOpBufferSize = 0; // In-order execution, always hide latency.
546 let LoadLatency = 3; // Expected cycles, may be overriden by OperandCycles. 22 let LoadLatency = 3; // Expected cycles, may be overriden.
547 let HighLatency = 30;// Expected, may be overriden by OperandCycles. 23 let HighLatency = 30;// Expected, may be overriden.
548 24
549 // On the Atom, the throughput for taken branches is 2 cycles. For small 25 // On the Atom, the throughput for taken branches is 2 cycles. For small
550 // simple loops, expand by a small factor to hide the backedge cost. 26 // simple loops, expand by a small factor to hide the backedge cost.
551 let LoopMicroOpBufferSize = 10; 27 let LoopMicroOpBufferSize = 10;
552 let PostRAScheduler = 1; 28 let PostRAScheduler = 1;
553 let CompleteModel = 0; 29 let CompleteModel = 0;
554 30 }
555 let Itineraries = AtomItineraries; 31
556 } 32 let SchedModel = AtomModel in {
33
34 // Functional Units
35 def AtomPort0 : ProcResource<1>; // ALU: ALU0, shift/rotate, load/store
36 // SIMD/FP: SIMD ALU, Shuffle,SIMD/FP multiply, divide
37 def AtomPort1 : ProcResource<1>; // ALU: ALU1, bit processing, jump, and LEA
38 // SIMD/FP: SIMD ALU, FP Adder
39
40 def AtomPort01 : ProcResGroup<[AtomPort0, AtomPort1]>;
41
42 // Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3
43 // cycles after the memory operand.
44 def : ReadAdvance<ReadAfterLd, 3>;
45 def : ReadAdvance<ReadAfterVecLd, 3>;
46 def : ReadAdvance<ReadAfterVecXLd, 3>;
47 def : ReadAdvance<ReadAfterVecYLd, 3>;
48
49 def : ReadAdvance<ReadInt2Fpu, 0>;
50
51 // Many SchedWrites are defined in pairs with and without a folded load.
52 // Instructions with folded loads are usually micro-fused, so they only appear
53 // as two micro-ops when dispatched by the schedulers.
54 // This multiclass defines the resource usage for variants with and without
55 // folded loads.
56 multiclass AtomWriteResPair<X86FoldableSchedWrite SchedRW,
57 list<ProcResourceKind> RRPorts,
58 list<ProcResourceKind> RMPorts,
59 int RRLat = 1, int RMLat = 1,
60 list<int> RRRes = [1],
61 list<int> RMRes = [1]> {
62 // Register variant is using a single cycle on ExePort.
63 def : WriteRes<SchedRW, RRPorts> {
64 let Latency = RRLat;
65 let ResourceCycles = RRRes;
66 }
67
68 // Memory variant also uses a cycle on JLAGU and adds 3 cycles to the
69 // latency.
70 def : WriteRes<SchedRW.Folded, RMPorts> {
71 let Latency = RMLat;
72 let ResourceCycles = RMRes;
73 }
74 }
75
76 // A folded store needs a cycle on Port0 for the store data.
77 def : WriteRes<WriteRMW, [AtomPort0]>;
78
79 ////////////////////////////////////////////////////////////////////////////////
80 // Arithmetic.
81 ////////////////////////////////////////////////////////////////////////////////
82
83 defm : AtomWriteResPair<WriteALU, [AtomPort01], [AtomPort0]>;
84 defm : AtomWriteResPair<WriteADC, [AtomPort01], [AtomPort0]>;
85
86 defm : AtomWriteResPair<WriteIMul8, [AtomPort01], [AtomPort01], 7, 7, [7], [7]>;
87 defm : AtomWriteResPair<WriteIMul16, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>;
88 defm : AtomWriteResPair<WriteIMul16Imm, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
89 defm : AtomWriteResPair<WriteIMul16Reg, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
90 defm : AtomWriteResPair<WriteIMul32, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
91 defm : AtomWriteResPair<WriteIMul32Imm, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
92 defm : AtomWriteResPair<WriteIMul32Reg, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
93 defm : AtomWriteResPair<WriteIMul64, [AtomPort01], [AtomPort01], 12, 12, [12], [12]>;
94 defm : AtomWriteResPair<WriteIMul64Imm, [AtomPort01], [AtomPort01], 14, 14, [14], [14]>;
95 defm : AtomWriteResPair<WriteIMul64Reg, [AtomPort01], [AtomPort01], 12, 12, [12], [12]>;
96 defm : X86WriteResUnsupported<WriteIMulH>;
97
98 defm : X86WriteRes<WriteXCHG, [AtomPort01], 2, [2], 1>;
99 defm : X86WriteRes<WriteBSWAP32, [AtomPort0], 1, [1], 1>;
100 defm : X86WriteRes<WriteBSWAP64, [AtomPort0], 1, [1], 1>;
101 defm : AtomWriteResPair<WriteCMPXCHG, [AtomPort01], [AtomPort01], 15, 15, [15]>;
102 defm : X86WriteRes<WriteCMPXCHGRMW, [AtomPort01, AtomPort0], 1, [1, 1], 1>;
103
104 defm : AtomWriteResPair<WriteDiv8, [AtomPort01], [AtomPort01], 50, 68, [50], [68]>;
105 defm : AtomWriteResPair<WriteDiv16, [AtomPort01], [AtomPort01], 50, 50, [50], [50]>;
106 defm : AtomWriteResPair<WriteDiv32, [AtomPort01], [AtomPort01], 50, 50, [50], [50]>;
107 defm : AtomWriteResPair<WriteDiv64, [AtomPort01], [AtomPort01],130,130,[130],[130]>;
108 defm : AtomWriteResPair<WriteIDiv8, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>;
109 defm : AtomWriteResPair<WriteIDiv16, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>;
110 defm : AtomWriteResPair<WriteIDiv32, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>;
111 defm : AtomWriteResPair<WriteIDiv64, [AtomPort01], [AtomPort01],130,130,[130],[130]>;
112
113 defm : X86WriteResPairUnsupported<WriteCRC32>;
114
115 defm : AtomWriteResPair<WriteCMOV, [AtomPort01], [AtomPort0]>;
116 defm : X86WriteRes<WriteFCMOV, [AtomPort01], 9, [9], 1>; // x87 conditional move.
117
118 def : WriteRes<WriteSETCC, [AtomPort01]>;
119 def : WriteRes<WriteSETCCStore, [AtomPort01]> {
120 let Latency = 2;
121 let ResourceCycles = [2];
122 }
123 def : WriteRes<WriteLAHFSAHF, [AtomPort01]> {
124 let Latency = 2;
125 let ResourceCycles = [2];
126 }
127 defm : X86WriteRes<WriteBitTest, [AtomPort1], 1, [1], 1>;
128 defm : X86WriteRes<WriteBitTestImmLd, [AtomPort0], 1, [1], 1>;
129 defm : X86WriteRes<WriteBitTestRegLd, [AtomPort01], 9, [9], 1>;
130 defm : X86WriteRes<WriteBitTestSet, [AtomPort1], 1, [1], 1>;
131 //defm : X86WriteRes<WriteBitTestSetImmLd, [AtomPort1], 1, [1], 1>;
132 //defm : X86WriteRes<WriteBitTestSetRegLd, [AtomPort1], 1, [1], 1>;
133
134 // This is for simple LEAs with one or two input operands.
135 def : WriteRes<WriteLEA, [AtomPort1]>;
136
137 // Bit counts.
138 defm : AtomWriteResPair<WriteBSF, [AtomPort01], [AtomPort01], 16, 16, [16], [16]>;
139 defm : AtomWriteResPair<WriteBSR, [AtomPort01], [AtomPort01], 16, 16, [16], [16]>;
140 defm : X86WriteResPairUnsupported<WritePOPCNT>;
141 defm : X86WriteResPairUnsupported<WriteLZCNT>;
142 defm : X86WriteResPairUnsupported<WriteTZCNT>;
143
144 // BMI1 BEXTR/BLS, BMI2 BZHI
145 defm : X86WriteResPairUnsupported<WriteBEXTR>;
146 defm : X86WriteResPairUnsupported<WriteBLS>;
147 defm : X86WriteResPairUnsupported<WriteBZHI>;
148
149 ////////////////////////////////////////////////////////////////////////////////
150 // Integer shifts and rotates.
151 ////////////////////////////////////////////////////////////////////////////////
152
153 defm : AtomWriteResPair<WriteShift, [AtomPort0], [AtomPort0]>;
154 defm : AtomWriteResPair<WriteShiftCL, [AtomPort0], [AtomPort0]>;
155 defm : AtomWriteResPair<WriteRotate, [AtomPort0], [AtomPort0]>;
156 defm : AtomWriteResPair<WriteRotateCL, [AtomPort0], [AtomPort0]>;
157
158 defm : X86WriteRes<WriteSHDrri, [AtomPort01], 2, [2], 1>;
159 defm : X86WriteRes<WriteSHDrrcl,[AtomPort01], 2, [2], 1>;
160 defm : X86WriteRes<WriteSHDmri, [AtomPort01], 4, [4], 1>;
161 defm : X86WriteRes<WriteSHDmrcl,[AtomPort01], 4, [4], 1>;
162
163 ////////////////////////////////////////////////////////////////////////////////
164 // Loads, stores, and moves, not folded with other operations.
165 ////////////////////////////////////////////////////////////////////////////////
166
167 def : WriteRes<WriteLoad, [AtomPort0]>;
168 def : WriteRes<WriteStore, [AtomPort0]>;
169 def : WriteRes<WriteStoreNT, [AtomPort0]>;
170 def : WriteRes<WriteMove, [AtomPort01]>;
171
172 // Treat misc copies as a move.
173 def : InstRW<[WriteMove], (instrs COPY)>;
174
175 ////////////////////////////////////////////////////////////////////////////////
176 // Idioms that clear a register, like xorps %xmm0, %xmm0.
177 // These can often bypass execution ports completely.
178 ////////////////////////////////////////////////////////////////////////////////
179
180 def : WriteRes<WriteZero, []>;
181
182 ////////////////////////////////////////////////////////////////////////////////
183 // Branches don't produce values, so they have no latency, but they still
184 // consume resources. Indirect branches can fold loads.
185 ////////////////////////////////////////////////////////////////////////////////
186
187 defm : AtomWriteResPair<WriteJump, [AtomPort1], [AtomPort1]>;
188
189 ////////////////////////////////////////////////////////////////////////////////
190 // Special case scheduling classes.
191 ////////////////////////////////////////////////////////////////////////////////
192
193 def : WriteRes<WriteSystem, [AtomPort01]> { let Latency = 100; }
194 def : WriteRes<WriteMicrocoded, [AtomPort01]> { let Latency = 100; }
195 def : WriteRes<WriteFence, [AtomPort0]>;
196
197 // Nops don't have dependencies, so there's no actual latency, but we set this
198 // to '1' to tell the scheduler that the nop uses an ALU slot for a cycle.
199 def : WriteRes<WriteNop, [AtomPort01]>;
200
201 ////////////////////////////////////////////////////////////////////////////////
202 // Floating point. This covers both scalar and vector operations.
203 ////////////////////////////////////////////////////////////////////////////////
204
205 defm : X86WriteRes<WriteFLD0, [AtomPort01], 1, [1], 1>;
206 defm : X86WriteRes<WriteFLD1, [AtomPort01], 6, [6], 1>;
207 def : WriteRes<WriteFLoad, [AtomPort0]>;
208 def : WriteRes<WriteFLoadX, [AtomPort0]>;
209 defm : X86WriteResUnsupported<WriteFLoadY>;
210 defm : X86WriteResUnsupported<WriteFMaskedLoad>;
211 defm : X86WriteResUnsupported<WriteFMaskedLoadY>;
212
213 def : WriteRes<WriteFStore, [AtomPort0]>;
214 def : WriteRes<WriteFStoreX, [AtomPort0]>;
215 defm : X86WriteResUnsupported<WriteFStoreY>;
216 def : WriteRes<WriteFStoreNT, [AtomPort0]>;
217 def : WriteRes<WriteFStoreNTX, [AtomPort0]>;
218 defm : X86WriteResUnsupported<WriteFStoreNTY>;
219 defm : X86WriteResUnsupported<WriteFMaskedStore>;
220 defm : X86WriteResUnsupported<WriteFMaskedStoreY>;
221
222 def : WriteRes<WriteFMove, [AtomPort01]>;
223 def : WriteRes<WriteFMoveX, [AtomPort01]>;
224 defm : X86WriteResUnsupported<WriteFMoveY>;
225
226 defm : X86WriteRes<WriteEMMS, [AtomPort01], 5, [5], 1>;
227
228 defm : AtomWriteResPair<WriteFAdd, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
229 defm : AtomWriteResPair<WriteFAddX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
230 defm : X86WriteResPairUnsupported<WriteFAddY>;
231 defm : X86WriteResPairUnsupported<WriteFAddZ>;
232 defm : AtomWriteResPair<WriteFAdd64, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
233 defm : AtomWriteResPair<WriteFAdd64X, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
234 defm : X86WriteResPairUnsupported<WriteFAdd64Y>;
235 defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
236 defm : AtomWriteResPair<WriteFCmp, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
237 defm : AtomWriteResPair<WriteFCmpX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
238 defm : X86WriteResPairUnsupported<WriteFCmpY>;
239 defm : X86WriteResPairUnsupported<WriteFCmpZ>;
240 defm : AtomWriteResPair<WriteFCmp64, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
241 defm : AtomWriteResPair<WriteFCmp64X, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
242 defm : X86WriteResPairUnsupported<WriteFCmp64Y>;
243 defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
244 defm : AtomWriteResPair<WriteFCom, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
245 defm : AtomWriteResPair<WriteFMul, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>;
246 defm : AtomWriteResPair<WriteFMulX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
247 defm : X86WriteResPairUnsupported<WriteFMulY>;
248 defm : X86WriteResPairUnsupported<WriteFMulZ>;
249 defm : AtomWriteResPair<WriteFMul64, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
250 defm : AtomWriteResPair<WriteFMul64X, [AtomPort01], [AtomPort01], 9, 10, [9], [10]>;
251 defm : X86WriteResPairUnsupported<WriteFMul64Y>;
252 defm : X86WriteResPairUnsupported<WriteFMul64Z>;
253 defm : AtomWriteResPair<WriteFRcp, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>;
254 defm : AtomWriteResPair<WriteFRcpX, [AtomPort01], [AtomPort01], 9, 10, [9], [10]>;
255 defm : X86WriteResPairUnsupported<WriteFRcpY>;
256 defm : X86WriteResPairUnsupported<WriteFRcpZ>;
257 defm : AtomWriteResPair<WriteFRsqrt, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>;
258 defm : AtomWriteResPair<WriteFRsqrtX, [AtomPort01], [AtomPort01], 9, 10, [9], [10]>;
259 defm : X86WriteResPairUnsupported<WriteFRsqrtY>;
260 defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
261 defm : AtomWriteResPair<WriteFDiv, [AtomPort01], [AtomPort01], 34, 34, [34], [34]>;
262 defm : AtomWriteResPair<WriteFDivX, [AtomPort01], [AtomPort01], 70, 70, [70], [70]>;
263 defm : X86WriteResPairUnsupported<WriteFDivY>;
264 defm : X86WriteResPairUnsupported<WriteFDivZ>;
265 defm : AtomWriteResPair<WriteFDiv64, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>;
266 defm : AtomWriteResPair<WriteFDiv64X, [AtomPort01], [AtomPort01],125,125,[125],[125]>;
267 defm : X86WriteResPairUnsupported<WriteFDiv64Y>;
268 defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
269 defm : AtomWriteResPair<WriteFSqrt, [AtomPort01], [AtomPort01], 34, 34, [34], [34]>;
270 defm : AtomWriteResPair<WriteFSqrtX, [AtomPort01], [AtomPort01], 70, 70, [70], [70]>;
271 defm : X86WriteResPairUnsupported<WriteFSqrtY>;
272 defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
273 defm : AtomWriteResPair<WriteFSqrt64, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>;
274 defm : AtomWriteResPair<WriteFSqrt64X, [AtomPort01], [AtomPort01],125,125,[125],[125]>;
275 defm : X86WriteResPairUnsupported<WriteFSqrt64Y>;
276 defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
277 defm : AtomWriteResPair<WriteFSqrt80, [AtomPort01], [AtomPort01], 71, 71, [71], [71]>;
278 defm : AtomWriteResPair<WriteFSign, [AtomPort1], [AtomPort1]>;
279 defm : AtomWriteResPair<WriteFRnd, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
280 defm : X86WriteResPairUnsupported<WriteFRndY>;
281 defm : X86WriteResPairUnsupported<WriteFRndZ>;
282 defm : AtomWriteResPair<WriteFLogic, [AtomPort01], [AtomPort0]>;
283 defm : X86WriteResPairUnsupported<WriteFLogicY>;
284 defm : X86WriteResPairUnsupported<WriteFLogicZ>;
285 defm : AtomWriteResPair<WriteFTest, [AtomPort01], [AtomPort0]>;
286 defm : X86WriteResPairUnsupported<WriteFTestY>;
287 defm : X86WriteResPairUnsupported<WriteFTestZ>;
288 defm : AtomWriteResPair<WriteFShuffle, [AtomPort0], [AtomPort0]>;
289 defm : X86WriteResPairUnsupported<WriteFShuffleY>;
290 defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
291 defm : X86WriteResPairUnsupported<WriteFVarShuffle>;
292 defm : X86WriteResPairUnsupported<WriteFVarShuffleY>;
293 defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
294 defm : X86WriteResPairUnsupported<WriteFMA>;
295 defm : X86WriteResPairUnsupported<WriteFMAX>;
296 defm : X86WriteResPairUnsupported<WriteFMAY>;
297 defm : X86WriteResPairUnsupported<WriteFMAZ>;
298 defm : X86WriteResPairUnsupported<WriteDPPD>;
299 defm : X86WriteResPairUnsupported<WriteDPPS>;
300 defm : X86WriteResPairUnsupported<WriteDPPSY>;
301 defm : X86WriteResPairUnsupported<WriteDPPSZ>;
302 defm : X86WriteResPairUnsupported<WriteFBlend>;
303 defm : X86WriteResPairUnsupported<WriteFBlendY>;
304 defm : X86WriteResPairUnsupported<WriteFBlendZ>;
305 defm : X86WriteResPairUnsupported<WriteFVarBlend>;
306 defm : X86WriteResPairUnsupported<WriteFVarBlendY>;
307 defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
308 defm : X86WriteResPairUnsupported<WriteFShuffle256>;
309 defm : X86WriteResPairUnsupported<WriteFVarShuffle256>;
310
311 ////////////////////////////////////////////////////////////////////////////////
312 // Conversions.
313 ////////////////////////////////////////////////////////////////////////////////
314
315 defm : AtomWriteResPair<WriteCvtSS2I, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>;
316 defm : AtomWriteResPair<WriteCvtPS2I, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
317 defm : X86WriteResPairUnsupported<WriteCvtPS2IY>;
318 defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
319 defm : AtomWriteResPair<WriteCvtSD2I, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>;
320 defm : AtomWriteResPair<WriteCvtPD2I, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>;
321 defm : X86WriteResPairUnsupported<WriteCvtPD2IY>;
322 defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
323
324 defm : AtomWriteResPair<WriteCvtI2SS, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
325 defm : AtomWriteResPair<WriteCvtI2PS, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
326 defm : X86WriteResPairUnsupported<WriteCvtI2PSY>;
327 defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
328 defm : AtomWriteResPair<WriteCvtI2SD, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
329 defm : AtomWriteResPair<WriteCvtI2PD, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>;
330 defm : X86WriteResPairUnsupported<WriteCvtI2PDY>;
331 defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
332
333 defm : AtomWriteResPair<WriteCvtSS2SD, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
334 defm : AtomWriteResPair<WriteCvtPS2PD, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>;
335 defm : X86WriteResPairUnsupported<WriteCvtPS2PDY>;
336 defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
337 defm : AtomWriteResPair<WriteCvtSD2SS, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
338 defm : AtomWriteResPair<WriteCvtPD2PS, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>;
339 defm : X86WriteResPairUnsupported<WriteCvtPD2PSY>;
340 defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
341
342 defm : X86WriteResPairUnsupported<WriteCvtPH2PS>;
343 defm : X86WriteResPairUnsupported<WriteCvtPH2PSY>;
344 defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>;
345 defm : X86WriteResUnsupported<WriteCvtPS2PH>;
346 defm : X86WriteResUnsupported<WriteCvtPS2PHSt>;
347 defm : X86WriteResUnsupported<WriteCvtPS2PHY>;
348 defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
349 defm : X86WriteResUnsupported<WriteCvtPS2PHYSt>;
350 defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
351
352 ////////////////////////////////////////////////////////////////////////////////
353 // Vector integer operations.
354 ////////////////////////////////////////////////////////////////////////////////
355
356 def : WriteRes<WriteVecLoad, [AtomPort0]>;
357 def : WriteRes<WriteVecLoadX, [AtomPort0]>;
358 defm : X86WriteResUnsupported<WriteVecLoadY>;
359 def : WriteRes<WriteVecLoadNT, [AtomPort0]>;
360 defm : X86WriteResUnsupported<WriteVecLoadNTY>;
361 defm : X86WriteResUnsupported<WriteVecMaskedLoad>;
362 defm : X86WriteResUnsupported<WriteVecMaskedLoadY>;
363
364 def : WriteRes<WriteVecStore, [AtomPort0]>;
365 def : WriteRes<WriteVecStoreX, [AtomPort0]>;
366 defm : X86WriteResUnsupported<WriteVecStoreY>;
367 def : WriteRes<WriteVecStoreNT, [AtomPort0]>;
368 defm : X86WriteResUnsupported<WriteVecStoreNTY>;
369 def : WriteRes<WriteVecMaskedStore, [AtomPort0]>;
370 defm : X86WriteResUnsupported<WriteVecMaskedStoreY>;
371
372 def : WriteRes<WriteVecMove, [AtomPort0]>;
373 def : WriteRes<WriteVecMoveX, [AtomPort01]>;
374 defm : X86WriteResUnsupported<WriteVecMoveY>;
375 defm : X86WriteRes<WriteVecMoveToGpr, [AtomPort0], 3, [3], 1>;
376 defm : X86WriteRes<WriteVecMoveFromGpr, [AtomPort0], 1, [1], 1>;
377
378 defm : AtomWriteResPair<WriteVecALU, [AtomPort01], [AtomPort0], 1, 1>;
379 defm : AtomWriteResPair<WriteVecALUX, [AtomPort01], [AtomPort0], 1, 1>;
380 defm : X86WriteResPairUnsupported<WriteVecALUY>;
381 defm : X86WriteResPairUnsupported<WriteVecALUZ>;
382 defm : AtomWriteResPair<WriteVecLogic, [AtomPort01], [AtomPort0], 1, 1>;
383 defm : AtomWriteResPair<WriteVecLogicX, [AtomPort01], [AtomPort0], 1, 1>;
384 defm : X86WriteResPairUnsupported<WriteVecLogicY>;
385 defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
386 defm : AtomWriteResPair<WriteVecTest, [AtomPort01], [AtomPort0], 1, 1>;
387 defm : X86WriteResPairUnsupported<WriteVecTestY>;
388 defm : X86WriteResPairUnsupported<WriteVecTestZ>;
389 defm : AtomWriteResPair<WriteVecShift, [AtomPort01], [AtomPort01], 2, 3, [2], [3]>;
390 defm : AtomWriteResPair<WriteVecShiftX, [AtomPort01], [AtomPort01], 2, 3, [2], [3]>;
391 defm : X86WriteResPairUnsupported<WriteVecShiftY>;
392 defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
393 defm : AtomWriteResPair<WriteVecShiftImm, [AtomPort01], [AtomPort01], 1, 1, [1], [1]>;
394 defm : AtomWriteResPair<WriteVecShiftImmX, [AtomPort01], [AtomPort01], 1, 1, [1], [1]>;
395 defm : X86WriteResPairUnsupported<WriteVecShiftImmY>;
396 defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
397 defm : AtomWriteResPair<WriteVecIMul, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>;
398 defm : AtomWriteResPair<WriteVecIMulX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
399 defm : X86WriteResPairUnsupported<WriteVecIMulY>;
400 defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
401 defm : X86WriteResPairUnsupported<WritePMULLD>;
402 defm : X86WriteResPairUnsupported<WritePMULLDY>;
403 defm : X86WriteResPairUnsupported<WritePMULLDZ>;
404 defm : X86WriteResPairUnsupported<WritePHMINPOS>;
405 defm : X86WriteResPairUnsupported<WriteMPSAD>;
406 defm : X86WriteResPairUnsupported<WriteMPSADY>;
407 defm : X86WriteResPairUnsupported<WriteMPSADZ>;
408 defm : AtomWriteResPair<WritePSADBW, [AtomPort01], [AtomPort01], 4, 4, [4], [4]>;
409 defm : AtomWriteResPair<WritePSADBWX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
410 defm : X86WriteResPairUnsupported<WritePSADBWY>;
411 defm : X86WriteResPairUnsupported<WritePSADBWZ>;
412 defm : AtomWriteResPair<WriteShuffle, [AtomPort0], [AtomPort0], 1, 1>;
413 defm : AtomWriteResPair<WriteShuffleX, [AtomPort0], [AtomPort0], 1, 1>;
414 defm : X86WriteResPairUnsupported<WriteShuffleY>;
415 defm : X86WriteResPairUnsupported<WriteShuffleZ>;
416 defm : AtomWriteResPair<WriteVarShuffle, [AtomPort0], [AtomPort0], 1, 1>;
417 defm : AtomWriteResPair<WriteVarShuffleX, [AtomPort01], [AtomPort01], 4, 5, [4], [5]>;
418 defm : X86WriteResPairUnsupported<WriteVarShuffleY>;
419 defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
420 defm : X86WriteResPairUnsupported<WriteBlend>;
421 defm : X86WriteResPairUnsupported<WriteBlendY>;
422 defm : X86WriteResPairUnsupported<WriteBlendZ>;
423 defm : X86WriteResPairUnsupported<WriteVarBlend>;
424 defm : X86WriteResPairUnsupported<WriteVarBlendY>;
425 defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
426 defm : X86WriteResPairUnsupported<WriteShuffle256>;
427 defm : X86WriteResPairUnsupported<WriteVarShuffle256>;
428 defm : X86WriteResPairUnsupported<WriteVarVecShift>;
429 defm : X86WriteResPairUnsupported<WriteVarVecShiftY>;
430 defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
431
432 ////////////////////////////////////////////////////////////////////////////////
433 // Vector insert/extract operations.
434 ////////////////////////////////////////////////////////////////////////////////
435
436 defm : AtomWriteResPair<WriteVecInsert, [AtomPort0], [AtomPort0], 1, 1>;
437 def : WriteRes<WriteVecExtract, [AtomPort0]>;
438 def : WriteRes<WriteVecExtractSt, [AtomPort0]>;
439
440 ////////////////////////////////////////////////////////////////////////////////
441 // SSE42 String instructions.
442 ////////////////////////////////////////////////////////////////////////////////
443
444 defm : X86WriteResPairUnsupported<WritePCmpIStrI>;
445 defm : X86WriteResPairUnsupported<WritePCmpIStrM>;
446 defm : X86WriteResPairUnsupported<WritePCmpEStrI>;
447 defm : X86WriteResPairUnsupported<WritePCmpEStrM>;
448
449 ////////////////////////////////////////////////////////////////////////////////
450 // MOVMSK Instructions.
451 ////////////////////////////////////////////////////////////////////////////////
452
453 def : WriteRes<WriteFMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
454 def : WriteRes<WriteVecMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
455 defm : X86WriteResUnsupported<WriteVecMOVMSKY>;
456 def : WriteRes<WriteMMXMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
457
458 ////////////////////////////////////////////////////////////////////////////////
459 // AES instructions.
460 ////////////////////////////////////////////////////////////////////////////////
461
462 defm : X86WriteResPairUnsupported<WriteAESIMC>;
463 defm : X86WriteResPairUnsupported<WriteAESKeyGen>;
464 defm : X86WriteResPairUnsupported<WriteAESDecEnc>;
465
466 ////////////////////////////////////////////////////////////////////////////////
467 // Horizontal add/sub instructions.
468 ////////////////////////////////////////////////////////////////////////////////
469
470 defm : AtomWriteResPair<WriteFHAdd, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>;
471 defm : AtomWriteResPair<WriteFHAddY, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>;
472 defm : AtomWriteResPair<WritePHAdd, [AtomPort01], [AtomPort01], 3, 4, [3], [4]>;
473 defm : AtomWriteResPair<WritePHAddX, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>;
474 defm : AtomWriteResPair<WritePHAddY, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>;
475
476 ////////////////////////////////////////////////////////////////////////////////
477 // Carry-less multiplication instructions.
478 ////////////////////////////////////////////////////////////////////////////////
479
480 defm : X86WriteResPairUnsupported<WriteCLMul>;
481
482 ////////////////////////////////////////////////////////////////////////////////
483 // Load/store MXCSR.
484 ////////////////////////////////////////////////////////////////////////////////
485
486 def : WriteRes<WriteLDMXCSR, [AtomPort01]> { let Latency = 5; let ResourceCycles = [5]; }
487 def : WriteRes<WriteSTMXCSR, [AtomPort01]> { let Latency = 15; let ResourceCycles = [15]; }
488
489 ////////////////////////////////////////////////////////////////////////////////
490 // Special Cases.
491 ////////////////////////////////////////////////////////////////////////////////
492
493 // Port0
494 def AtomWrite0_1 : SchedWriteRes<[AtomPort0]> {
495 let Latency = 1;
496 let ResourceCycles = [1];
497 }
498 def : InstRW<[AtomWrite0_1], (instrs FXAM, LD_Frr,
499 MOVSX64rr32)>;
500 def : SchedAlias<WriteALURMW, AtomWrite0_1>;
501 def : SchedAlias<WriteADCRMW, AtomWrite0_1>;
502 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
503 "MOV(S|Z)X(32|64)rr(8|8_NOREX|16)")>;
504
505 // Port1
506 def AtomWrite1_1 : SchedWriteRes<[AtomPort1]> {
507 let Latency = 1;
508 let ResourceCycles = [1];
509 }
510 def : InstRW<[AtomWrite1_1], (instrs FCOMPP)>;
511 def : InstRW<[AtomWrite1_1], (instregex "UCOM_F(P|PP)?r")>;
512
513 def AtomWrite1_5 : SchedWriteRes<[AtomPort1]> {
514 let Latency = 5;
515 let ResourceCycles = [5];
516 }
517 def : InstRW<[AtomWrite1_5], (instrs MMX_CVTPI2PSirr, MMX_CVTPI2PSirm,
518 MMX_CVTPS2PIirr, MMX_CVTTPS2PIirr)>;
519
520 // Port0 and Port1
521 def AtomWrite0_1_1 : SchedWriteRes<[AtomPort0, AtomPort1]> {
522 let Latency = 1;
523 let ResourceCycles = [1, 1];
524 }
525 def : InstRW<[AtomWrite0_1_1], (instrs POP32r, POP64r,
526 POP16rmr, POP32rmr, POP64rmr,
527 PUSH16r, PUSH32r, PUSH64r,
528 PUSHi16, PUSHi32,
529 PUSH16rmr, PUSH32rmr, PUSH64rmr,
530 PUSH16i8, PUSH32i8, PUSH64i8, PUSH64i32,
531 XCH_F)>;
532 def : InstRW<[AtomWrite0_1_1], (instregex "RETI(L|Q|W)$",
533 "IRET(16|32|64)?")>;
534
535 def AtomWrite0_1_5 : SchedWriteRes<[AtomPort0, AtomPort1]> {
536 let Latency = 5;
537 let ResourceCycles = [5, 5];
538 }
539 def : InstRW<[AtomWrite0_1_5], (instrs MMX_CVTPS2PIirm, MMX_CVTTPS2PIirm)>;
540 def : InstRW<[AtomWrite0_1_5], (instregex "ILD_F(16|32|64)")>;
541
542 // Port0 or Port1
543 def AtomWrite01_1 : SchedWriteRes<[AtomPort01]> {
544 let Latency = 1;
545 let ResourceCycles = [1];
546 }
547 def : InstRW<[AtomWrite01_1], (instrs FDECSTP, FFREE, FFREEP, FINCSTP, WAIT,
548 LFENCE,
549 STOSB, STOSL, STOSQ, STOSW,
550 MOVSSrr, MOVSSrr_REV,
551 PSLLDQri, PSRLDQri)>;
552 def : InstRW<[AtomWrite01_1], (instregex "MMX_PACK(SSDW|SSWB|USWB)irr",
553 "MMX_PUNPCKH(BW|DQ|WD)irr")>;
554
555 def AtomWrite01_2 : SchedWriteRes<[AtomPort01]> {
556 let Latency = 2;
557 let ResourceCycles = [2];
558 }
559 def : InstRW<[AtomWrite01_2], (instrs LEAVE, LEAVE64, POP16r,
560 PUSH16rmm, PUSH32rmm, PUSH64rmm,
561 LODSB, LODSL, LODSQ, LODSW,
562 SCASB, SCASL, SCASQ, SCASW)>;
563 def : InstRW<[AtomWrite01_2], (instregex "PUSH(CS|DS|ES|FS|GS|SS)(16|32|64)",
564 "(ST|ISTT)_F(P)?(16|32|64)?(m|rr)",
565 "MMX_P(ADD|SUB)Qirr",
566 "MOV(S|Z)X16rr8",
567 "MOV(UPS|UPD|DQU)mr",
568 "MASKMOVDQU(64)?",
569 "P(ADD|SUB)Qrr")>;
570 def : SchedAlias<WriteBitTestSetImmRMW, AtomWrite01_2>;
571
572 def AtomWrite01_3 : SchedWriteRes<[AtomPort01]> {
573 let Latency = 3;
574 let ResourceCycles = [3];
575 }
576 def : InstRW<[AtomWrite01_3], (instrs CLD, LDDQUrm,
577 CMPSB, CMPSL, CMPSQ, CMPSW,
578 MOVSB, MOVSL, MOVSQ, MOVSW,
579 POP16rmm, POP32rmm, POP64rmm)>;
580 def : InstRW<[AtomWrite01_3], (instregex "XADD(8|16|32|64)rm",
581 "XCHG(8|16|32|64)rm",
582 "PH(ADD|SUB)Drr",
583 "MOV(S|Z)X16rm8",
584 "MMX_P(ADD|SUB)Qirm",
585 "MOV(UPS|UPD|DQU)rm",
586 "P(ADD|SUB)Qrm")>;
587
588 def AtomWrite01_4 : SchedWriteRes<[AtomPort01]> {
589 let Latency = 4;
590 let ResourceCycles = [4];
591 }
592 def : InstRW<[AtomWrite01_4], (instrs CBW, CWD, CWDE, CDQ, CDQE, CQO,
593 JCXZ, JECXZ, JRCXZ,
594 LD_F80m)>;
595 def : InstRW<[AtomWrite01_4], (instregex "PH(ADD|SUB)Drm",
596 "(MMX_)?PEXTRWrr(_REV)?")>;
597
598 def AtomWrite01_5 : SchedWriteRes<[AtomPort01]> {
599 let Latency = 5;
600 let ResourceCycles = [5];
601 }
602 def : InstRW<[AtomWrite01_5], (instrs FLDCW16m, ST_FP80m)>;
603 def : InstRW<[AtomWrite01_5], (instregex "MMX_PH(ADD|SUB)S?Wrr")>;
604
605 def AtomWrite01_6 : SchedWriteRes<[AtomPort01]> {
606 let Latency = 6;
607 let ResourceCycles = [6];
608 }
609 def : InstRW<[AtomWrite01_6], (instrs CMPXCHG8rm, INTO, XLAT,
610 SHLD16rrCL, SHRD16rrCL,
611 SHLD16rri8, SHRD16rri8,
612 SHLD16mrCL, SHRD16mrCL,
613 SHLD16mri8, SHRD16mri8)>;
614 def : InstRW<[AtomWrite01_6], (instregex "IST_F(P)?(16|32|64)?m",
615 "MMX_PH(ADD|SUB)S?Wrm")>;
616
617 def AtomWrite01_7 : SchedWriteRes<[AtomPort01]> {
618 let Latency = 7;
619 let ResourceCycles = [7];
620 }
621 def : InstRW<[AtomWrite01_7], (instrs AAD8i8)>;
622
623 def AtomWrite01_8 : SchedWriteRes<[AtomPort01]> {
624 let Latency = 8;
625 let ResourceCycles = [8];
626 }
627 def : InstRW<[AtomWrite01_8], (instrs LOOPE,
628 PUSHA16, PUSHA32,
629 SHLD64rrCL, SHRD64rrCL,
630 FNSTCW16m)>;
631
632 def AtomWrite01_9 : SchedWriteRes<[AtomPort01]> {
633 let Latency = 9;
634 let ResourceCycles = [9];
635 }
636 def : InstRW<[AtomWrite01_9], (instrs POPA16, POPA32,
637 PUSHF16, PUSHF32, PUSHF64,
638 SHLD64mrCL, SHRD64mrCL,
639 SHLD64mri8, SHRD64mri8,
640 SHLD64rri8, SHRD64rri8,
641 CMPXCHG8rr)>;
642 def : InstRW<[AtomWrite01_9], (instregex "(U)?COM_FI", "TST_F",
643 "(U)?COMIS(D|S)rr",
644 "CVT(T)?SS2SI64rr(_Int)?")>;
645
646 def AtomWrite01_10 : SchedWriteRes<[AtomPort01]> {
647 let Latency = 10;
648 let ResourceCycles = [10];
649 }
650 def : SchedAlias<WriteFLDC, AtomWrite01_10>;
651 def : InstRW<[AtomWrite01_10], (instregex "(U)?COMIS(D|S)rm",
652 "CVT(T)?SS2SI64rm(_Int)?")>;
653
654 def AtomWrite01_11 : SchedWriteRes<[AtomPort01]> {
655 let Latency = 11;
656 let ResourceCycles = [11];
657 }
658 def : InstRW<[AtomWrite01_11], (instrs BOUNDS16rm, BOUNDS32rm)>;
659 def : SchedAlias<WriteBitTestSetRegRMW, AtomWrite01_11>;
660
661 def AtomWrite01_13 : SchedWriteRes<[AtomPort01]> {
662 let Latency = 13;
663 let ResourceCycles = [13];
664 }
665 def : InstRW<[AtomWrite01_13], (instrs AAA, AAS)>;
666
667 def AtomWrite01_14 : SchedWriteRes<[AtomPort01]> {
668 let Latency = 14;
669 let ResourceCycles = [14];
670 }
671 def : InstRW<[AtomWrite01_14], (instrs CMPXCHG16rm, CMPXCHG32rm, CMPXCHG64rm)>;
672
673 def AtomWrite01_17 : SchedWriteRes<[AtomPort01]> {
674 let Latency = 17;
675 let ResourceCycles = [17];
676 }
677 def : InstRW<[AtomWrite01_17], (instrs LOOPNE, PAUSE)>;
678
679 def AtomWrite01_18 : SchedWriteRes<[AtomPort01]> {
680 let Latency = 18;
681 let ResourceCycles = [18];
682 }
683 def : InstRW<[AtomWrite01_18], (instrs CMPXCHG8B, DAA, LOOP)>;
684
685 def AtomWrite01_20 : SchedWriteRes<[AtomPort01]> {
686 let Latency = 20;
687 let ResourceCycles = [20];
688 }
689 def : InstRW<[AtomWrite01_20], (instrs DAS)>;
690
691 def AtomWrite01_21 : SchedWriteRes<[AtomPort01]> {
692 let Latency = 21;
693 let ResourceCycles = [21];
694 }
695 def : InstRW<[AtomWrite01_21], (instrs AAM8i8, STD)>;
696
697 def AtomWrite01_22 : SchedWriteRes<[AtomPort01]> {
698 let Latency = 22;
699 let ResourceCycles = [22];
700 }
701 def : InstRW<[AtomWrite01_22], (instrs CMPXCHG16B)>;
702
703 def AtomWrite01_23 : SchedWriteRes<[AtomPort01]> {
704 let Latency = 23;
705 let ResourceCycles = [23];
706 }
707 def : InstRW<[AtomWrite01_23], (instrs ARPL16mr, ARPL16rr)>;
708
709 def AtomWrite01_25 : SchedWriteRes<[AtomPort01]> {
710 let Latency = 25;
711 let ResourceCycles = [25];
712 }
713 def : InstRW<[AtomWrite01_25], (instrs FNCLEX, FXTRACT)>;
714
715 def AtomWrite01_26 : SchedWriteRes<[AtomPort01]> {
716 let Latency = 26;
717 let ResourceCycles = [26];
718 }
719 def : InstRW<[AtomWrite01_26], (instrs POPF32, POPF64)>;
720
721 def AtomWrite01_29 : SchedWriteRes<[AtomPort01]> {
722 let Latency = 29;
723 let ResourceCycles = [29];
724 }
725 def : InstRW<[AtomWrite01_29], (instregex "POP(DS|ES|FS|GS)(16|32|64)")>;
726
727 def AtomWrite01_30 : SchedWriteRes<[AtomPort01]> {
728 let Latency = 30;
729 let ResourceCycles = [30];
730 }
731 def : InstRW<[AtomWrite01_30], (instrs RDTSC, RDTSCP)>;
732
733 def AtomWrite01_32 : SchedWriteRes<[AtomPort01]> {
734 let Latency = 32;
735 let ResourceCycles = [32];
736 }
737 def : InstRW<[AtomWrite01_32], (instrs ENTER, POPF16)>;
738
739 def AtomWrite01_45 : SchedWriteRes<[AtomPort01]> {
740 let Latency = 45;
741 let ResourceCycles = [45];
742 }
743 def : InstRW<[AtomWrite01_45], (instrs MONITOR32rrr, MONITOR64rrr)>;
744
745 def AtomWrite01_46 : SchedWriteRes<[AtomPort01]> {
746 let Latency = 46;
747 let ResourceCycles = [46];
748 }
749 def : InstRW<[AtomWrite01_46], (instrs FRNDINT, MWAITrr, RDPMC)>;
750
751 def AtomWrite01_48 : SchedWriteRes<[AtomPort01]> {
752 let Latency = 48;
753 let ResourceCycles = [48];
754 }
755 def : InstRW<[AtomWrite01_48], (instrs POPSS16, POPSS32)>;
756
757 def AtomWrite01_55 : SchedWriteRes<[AtomPort01]> {
758 let Latency = 55;
759 let ResourceCycles = [55];
760 }
761 def : InstRW<[AtomWrite01_55], (instrs FPREM)>;
762
763 def AtomWrite01_59 : SchedWriteRes<[AtomPort01]> {
764 let Latency = 59;
765 let ResourceCycles = [59];
766 }
767 def : InstRW<[AtomWrite01_59], (instrs INSB, INSL, INSW)>;
768
769 def AtomWrite01_63 : SchedWriteRes<[AtomPort01]> {
770 let Latency = 63;
771 let ResourceCycles = [63];
772 }
773 def : InstRW<[AtomWrite01_63], (instrs FNINIT)>;
774
775 def AtomWrite01_68 : SchedWriteRes<[AtomPort01]> {
776 let Latency = 68;
777 let ResourceCycles = [68];
778 }
779 def : InstRW<[AtomWrite01_68], (instrs OUT8rr, OUT16rr, OUT32rr)>;
780
781 def AtomWrite01_71 : SchedWriteRes<[AtomPort01]> {
782 let Latency = 71;
783 let ResourceCycles = [71];
784 }
785 def : InstRW<[AtomWrite01_71], (instrs FPREM1,
786 INVLPG, INVLPGA32, INVLPGA64)>;
787
788 def AtomWrite01_72 : SchedWriteRes<[AtomPort01]> {
789 let Latency = 72;
790 let ResourceCycles = [72];
791 }
792 def : InstRW<[AtomWrite01_72], (instrs OUT8ir, OUT16ir, OUT32ir)>;
793
794 def AtomWrite01_74 : SchedWriteRes<[AtomPort01]> {
795 let Latency = 74;
796 let ResourceCycles = [74];
797 }
798 def : InstRW<[AtomWrite01_74], (instrs OUTSB, OUTSL, OUTSW)>;
799
800 def AtomWrite01_77 : SchedWriteRes<[AtomPort01]> {
801 let Latency = 77;
802 let ResourceCycles = [77];
803 }
804 def : InstRW<[AtomWrite01_77], (instrs FSCALE)>;
805
806 def AtomWrite01_78 : SchedWriteRes<[AtomPort01]> {
807 let Latency = 78;
808 let ResourceCycles = [78];
809 }
810 def : InstRW<[AtomWrite01_78], (instrs RDMSR)>;
811
812 def AtomWrite01_79 : SchedWriteRes<[AtomPort01]> {
813 let Latency = 79;
814 let ResourceCycles = [79];
815 }
816 def : InstRW<[AtomWrite01_79], (instregex "RET(L|Q|W)?$",
817 "LRETI?(L|Q|W)")>;
818
819 def AtomWrite01_92 : SchedWriteRes<[AtomPort01]> {
820 let Latency = 92;
821 let ResourceCycles = [92];
822 }
823 def : InstRW<[AtomWrite01_92], (instrs IN8ri, IN16ri, IN32ri)>;
824
825 def AtomWrite01_94 : SchedWriteRes<[AtomPort01]> {
826 let Latency = 94;
827 let ResourceCycles = [94];
828 }
829 def : InstRW<[AtomWrite01_94], (instrs IN8rr, IN16rr, IN32rr)>;
830
831 def AtomWrite01_99 : SchedWriteRes<[AtomPort01]> {
832 let Latency = 99;
833 let ResourceCycles = [99];
834 }
835 def : InstRW<[AtomWrite01_99], (instrs F2XM1)>;
836
837 def AtomWrite01_121 : SchedWriteRes<[AtomPort01]> {
838 let Latency = 121;
839 let ResourceCycles = [121];
840 }
841 def : InstRW<[AtomWrite01_121], (instrs CPUID)>;
842
843 def AtomWrite01_127 : SchedWriteRes<[AtomPort01]> {
844 let Latency = 127;
845 let ResourceCycles = [127];
846 }
847 def : InstRW<[AtomWrite01_127], (instrs INT)>;
848
849 def AtomWrite01_130 : SchedWriteRes<[AtomPort01]> {
850 let Latency = 130;
851 let ResourceCycles = [130];
852 }
853 def : InstRW<[AtomWrite01_130], (instrs INT3)>;
854
855 def AtomWrite01_140 : SchedWriteRes<[AtomPort01]> {
856 let Latency = 140;
857 let ResourceCycles = [140];
858 }
859 def : InstRW<[AtomWrite01_140], (instrs FXSAVE, FXSAVE64)>;
860
861 def AtomWrite01_141 : SchedWriteRes<[AtomPort01]> {
862 let Latency = 141;
863 let ResourceCycles = [141];
864 }
865 def : InstRW<[AtomWrite01_141], (instrs FXRSTOR, FXRSTOR64)>;
866
867 def AtomWrite01_146 : SchedWriteRes<[AtomPort01]> {
868 let Latency = 146;
869 let ResourceCycles = [146];
870 }
871 def : InstRW<[AtomWrite01_146], (instrs FYL2X)>;
872
873 def AtomWrite01_147 : SchedWriteRes<[AtomPort01]> {
874 let Latency = 147;
875 let ResourceCycles = [147];
876 }
877 def : InstRW<[AtomWrite01_147], (instrs FYL2XP1)>;
878
879 def AtomWrite01_168 : SchedWriteRes<[AtomPort01]> {
880 let Latency = 168;
881 let ResourceCycles = [168];
882 }
883 def : InstRW<[AtomWrite01_168], (instrs FPTAN)>;
884
885 def AtomWrite01_174 : SchedWriteRes<[AtomPort01]> {
886 let Latency = 174;
887 let ResourceCycles = [174];
888 }
889 def : InstRW<[AtomWrite01_174], (instrs FSINCOS)>;
890 def : InstRW<[AtomWrite01_174], (instregex "(COS|SIN)_F")>;
891
892 def AtomWrite01_183 : SchedWriteRes<[AtomPort01]> {
893 let Latency = 183;
894 let ResourceCycles = [183];
895 }
896 def : InstRW<[AtomWrite01_183], (instrs FPATAN)>;
897
898 def AtomWrite01_202 : SchedWriteRes<[AtomPort01]> {
899 let Latency = 202;
900 let ResourceCycles = [202];
901 }
902 def : InstRW<[AtomWrite01_202], (instrs WRMSR)>;
903
904 } // SchedModel