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comparison lib/Target/Mips/Mips16ISelDAGToDAG.cpp @ 100:7d135dc70f03 LLVM 3.9

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children 1172e4bd9c6f
comparison
equal deleted inserted replaced
96:6418606d0ead 100:7d135dc70f03
71 71
72 MachineBasicBlock &MBB = MF.front(); 72 MachineBasicBlock &MBB = MF.front();
73 MachineBasicBlock::iterator I = MBB.begin(); 73 MachineBasicBlock::iterator I = MBB.begin();
74 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 74 MachineRegisterInfo &RegInfo = MF.getRegInfo();
75 const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); 75 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
76 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); 76 DebugLoc DL;
77 unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(); 77 unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();
78 const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass; 78 const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass;
79 79
80 V0 = RegInfo.createVirtualRegister(RC); 80 V0 = RegInfo.createVirtualRegister(RC);
81 V1 = RegInfo.createVirtualRegister(RC); 81 V1 = RegInfo.createVirtualRegister(RC);