CbC/CbC_llvm: lib/Target/Mips/MipsInstrInfo.td comparison

comparison lib/Target/Mips/MipsInstrInfo.td @ 100:7d135dc70f03 LLVM 3.9

LLVM 3.9

author	Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date	Tue, 26 Jan 2016 22:53:40 +0900
parents	afa8332a0e37
children	1172e4bd9c6f

comparison

equal deleted inserted replaced

-:6418606d0ead
+:7d135dc70f03
 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
 // Return
 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
+def MipsERet : SDNode<"MipsISD::ERet", SDTNone,
+[SDNPHasChain, SDNPOptInGlue, SDNPSideEffect]>;
 // These are target-independent nodes, but have target-specific formats.
 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
 def callseq_end   : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
 AssemblerPredicate<"FeatureGP64Bit">;
 def IsGP32bit    :    Predicate<"!Subtarget->isGP64bit()">,
 AssemblerPredicate<"!FeatureGP64Bit">;
 def HasMips64    :    Predicate<"Subtarget->hasMips64()">,
 AssemblerPredicate<"FeatureMips64">;
+def NotMips64    :    Predicate<"!Subtarget->hasMips64()">,
+AssemblerPredicate<"!FeatureMips64">;
 def HasMips64r2  :    Predicate<"Subtarget->hasMips64r2()">,
 AssemblerPredicate<"FeatureMips64r2">;
 def HasMips64r6  :    Predicate<"Subtarget->hasMips64r6()">,
 AssemblerPredicate<"FeatureMips64r6">;
 def NotMips64r6  :    Predicate<"!Subtarget->hasMips64r6()">,
 // MIPS32r6 and MIPS64r6.
 class INSN_MIPS5_32R2_NOT_32R6_64R6 {
 list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
 }
+class ASE_CNMIPS {
+list<Predicate> InsnPredicates = [HasCnMips];
+}
 class ASE_MSA {
 list<Predicate> InsnPredicates = [HasMSA];
+}
+class ASE_MSA_NOT_MSA64 {
+list<Predicate> InsnPredicates = [HasMSA, NotMips64];
 }
 class ASE_MSA64 {
 list<Predicate> InsnPredicates = [HasMSA, HasMips64];
 }
 //===----------------------------------------------------------------------===//
 // Mips Operand, Complex Patterns and Transformations Definitions.
 //===----------------------------------------------------------------------===//
+class ConstantSImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []>
+: AsmOperandClass {
+let Name = "ConstantSImm" # Bits;
+let RenderMethod = "addImmOperands";
+let PredicateMethod = "isConstantSImm<" # Bits # ">";
+let SuperClasses = Supers;
+let DiagnosticType = "SImm" # Bits;
+}
+class ConstantUImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = [],
+int Offset = 0> : AsmOperandClass {
+let Name = "ConstantUImm" # Bits # "_" # Offset;
+let RenderMethod = "addConstantUImmOperands<" # Bits # ", " # Offset # ">";
+let PredicateMethod = "isConstantUImm<" # Bits # ", " # Offset # ">";
+let SuperClasses = Supers;
+let DiagnosticType = "UImm" # Bits # "_" # Offset;
+}
+def ConstantUImm10AsmOperandClass
+: ConstantUImmAsmOperandClass<10, []>;
+def ConstantUImm8AsmOperandClass
+: ConstantUImmAsmOperandClass<8, [ConstantUImm10AsmOperandClass]>;
+def ConstantUImm7AsmOperandClass
+: ConstantUImmAsmOperandClass<7, [ConstantUImm8AsmOperandClass]>;
+def ConstantUImm6AsmOperandClass
+: ConstantUImmAsmOperandClass<6, [ConstantUImm7AsmOperandClass]>;
+def ConstantSImm6AsmOperandClass
+: ConstantSImmAsmOperandClass<6, [ConstantUImm7AsmOperandClass]>;
+def ConstantUImm5Plus1AsmOperandClass
+: ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass], 1>;
+def ConstantUImm5Plus32AsmOperandClass
+: ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass], 32>;
+def ConstantUImm5Plus33AsmOperandClass
+: ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass], 33>;
+def ConstantUImm5Plus32NormalizeAsmOperandClass
+: ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass], 32> {
+let Name = "ConstantUImm5_32_Norm";
+// We must also subtract 32 when we render the operand.
+let RenderMethod = "addConstantUImmOperands<5, 32, -32>";
+}
+def ConstantUImm5Lsl2AsmOperandClass : AsmOperandClass {
+let Name = "UImm5Lsl2";
+let RenderMethod = "addImmOperands";
+let PredicateMethod = "isScaledUImm<5, 2>";
+let SuperClasses = [ConstantUImm6AsmOperandClass];
+let DiagnosticType = "UImm5_Lsl2";
+}
+def ConstantUImm5ReportUImm6AsmOperandClass
+: ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass]> {
+let Name = "ConstantUImm5_0_Report_UImm6";
+let DiagnosticType = "UImm5_0_Report_UImm6";
+}
+def ConstantUImm5AsmOperandClass
+: ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass]>;
+def ConstantUImm4AsmOperandClass
+: ConstantUImmAsmOperandClass<
+4, [ConstantUImm5AsmOperandClass,
+ConstantUImm5Plus32AsmOperandClass,
+ConstantUImm5Plus32NormalizeAsmOperandClass]>;
+def ConstantUImm3AsmOperandClass
+: ConstantUImmAsmOperandClass<3, [ConstantUImm4AsmOperandClass]>;
+def ConstantUImm2Plus1AsmOperandClass
+: ConstantUImmAsmOperandClass<2, [ConstantUImm3AsmOperandClass], 1>;
+def ConstantUImm2AsmOperandClass
+: ConstantUImmAsmOperandClass<2, [ConstantUImm3AsmOperandClass]>;
+def ConstantUImm1AsmOperandClass
+: ConstantUImmAsmOperandClass<1, [ConstantUImm2AsmOperandClass]>;
+def ConstantImmzAsmOperandClass : AsmOperandClass {
+let Name = "ConstantImmz";
+let RenderMethod = "addConstantUImmOperands<1>";
+let PredicateMethod = "isConstantImmz";
+let SuperClasses = [ConstantUImm1AsmOperandClass];
+let DiagnosticType = "Immz";
+}
 def MipsJumpTargetAsmOperand : AsmOperandClass {
 let Name = "JumpTarget";
 let ParserMethod = "parseJumpTarget";
 let PredicateMethod = "isImm";
 let RenderMethod = "addImmOperands";
 let ParserMatchClass = MipsJumpTargetAsmOperand;
 }
 def imm64: Operand<i64>;
+def simm6 : Operand<i32> {
+let ParserMatchClass = ConstantSImm6AsmOperandClass;
+let OperandType = "OPERAND_IMMEDIATE";
+}
 def simm9 : Operand<i32>;
 def simm10 : Operand<i32>;
 def simm11 : Operand<i32>;
 def simm16      : Operand<i32> {
 let EncoderMethod = "getSimm18Lsl3Encoding";
 let DecoderMethod = "DecodeSimm18Lsl3";
 let ParserMatchClass = MipsJumpTargetAsmOperand;
 }
-def simm20      : Operand<i32> {
+def simm20      : Operand<i32>;
-}
+def simm32      : Operand<i32>;
 def uimm20      : Operand<i32> {
-}
-def MipsUImm10AsmOperand : AsmOperandClass {
-let Name = "UImm10";
-let RenderMethod = "addImmOperands";
-let ParserMethod = "parseImm";
-let PredicateMethod = "isUImm<10>";
-}
-def uimm10      : Operand<i32> {
-let ParserMatchClass = MipsUImm10AsmOperand;
 }
 def simm16_64   : Operand<i64> {
 let DecoderMethod = "DecodeSimm16";
 }
 // Zero
 def uimmz       : Operand<i32> {
 let PrintMethod = "printUnsignedImm";
-}
+let ParserMatchClass = ConstantImmzAsmOperandClass;
+}
-// Unsigned Operand
-def uimm2 : Operand<i32> {
+// Unsigned Operands
+foreach I = {1, 2, 3, 4, 5, 6, 7, 8, 10} in
+def uimm # I : Operand<i32> {
+let PrintMethod = "printUnsignedImm";
+let ParserMatchClass =
+!cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass");
+}
+def uimm2_plus1 : Operand<i32> {
 let PrintMethod = "printUnsignedImm";
-}
+let EncoderMethod = "getUImmWithOffsetEncoding<2, 1>";
+let DecoderMethod = "DecodeUImmWithOffset<2, 1>";
-def uimm3 : Operand<i32> {
+let ParserMatchClass = ConstantUImm2Plus1AsmOperandClass;
+}
+def uimm5_plus1 : Operand<i32> {
 let PrintMethod = "printUnsignedImm";
-}
+let EncoderMethod = "getUImmWithOffsetEncoding<5, 1>";
+let DecoderMethod = "DecodeUImmWithOffset<5, 1>";
-def uimm5       : Operand<i32> {
+let ParserMatchClass = ConstantUImm5Plus1AsmOperandClass;
+}
+def uimm5_plus32 : Operand<i32> {
 let PrintMethod = "printUnsignedImm";
-}
+let ParserMatchClass = ConstantUImm5Plus32AsmOperandClass;
+}
-def uimm6 : Operand<i32> {
+def uimm5_plus33 : Operand<i32> {
 let PrintMethod = "printUnsignedImm";
+let EncoderMethod = "getUImmWithOffsetEncoding<5, 1>";
+let DecoderMethod = "DecodeUImmWithOffset<5, 1>";
+let ParserMatchClass = ConstantUImm5Plus33AsmOperandClass;
+}
+def uimm5_plus32_normalize : Operand<i32> {
+let PrintMethod = "printUnsignedImm";
+let ParserMatchClass = ConstantUImm5Plus32NormalizeAsmOperandClass;
+}
+def uimm5_lsl2 : Operand<OtherVT> {
+let EncoderMethod = "getUImm5Lsl2Encoding";
+let DecoderMethod = "DecodeUImm5lsl2";
+let ParserMatchClass = ConstantUImm5Lsl2AsmOperandClass;
+}
+def uimm5_plus32_normalize_64 : Operand<i64> {
+let PrintMethod = "printUnsignedImm";
+let ParserMatchClass = ConstantUImm5Plus32NormalizeAsmOperandClass;
+}
+foreach I = {5} in
+def uimm # I # _64 : Operand<i64> {
+let PrintMethod = "printUnsignedImm";
+let ParserMatchClass =
+!cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass");
+}
+// Like uimm5_64 but reports a less confusing error for 32-63 when
+// an instruction alias permits that.
+def uimm5_64_report_uimm6 : Operand<i64> {
+let PrintMethod = "printUnsignedImm";
+let ParserMatchClass = ConstantUImm5ReportUImm6AsmOperandClass;
 }
 def uimm16      : Operand<i32> {
 let PrintMethod = "printUnsignedImm";
 }
 def PtrRC : Operand<iPTR> {
 let MIOperandInfo = (ops ptr_rc);
 let DecoderMethod = "DecodePtrRegisterClass";
 let ParserMatchClass = GPR32AsmOperand;
-}
-// size operand of ext instruction
-def size_ext : Operand<i32> {
-let EncoderMethod = "getSizeExtEncoding";
-let DecoderMethod = "DecodeExtSize";
 }
 // size operand of ins instruction
 def size_ins : Operand<i32> {
 let EncoderMethod = "getSizeInsEncoding";
 // Jump and Link (Call)
 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
 class JumpLink<string opstr, DAGOperand opnd> :
 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
-[(MipsJmpLink imm:$target)], II_JAL, FrmJ, opstr> {
+[(MipsJmpLink tglobaladdr:$target)], II_JAL, FrmJ, opstr> {
 let DecoderMethod = "DecodeJumpTarget";
 }
 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
 Register RetReg, RegisterOperand ResRO = RO>:
 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
 II_RDHWR, FrmR, "rdhwr">;
 // Ext and Ins
 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
-SDPatternOperator Op = null_frag>:
+Operand SizeOpnd, SDPatternOperator Op = null_frag> :
-InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
+InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size),
 !strconcat(opstr, " $rt, $rs, $pos, $size"),
 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], II_EXT,
 FrmR, opstr>, ISA_MIPS32R2;
 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
 //===----------------------------------------------------------------------===//
 // Return RA.
 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
+let isReturn=1, isTerminator=1, isBarrier=1, hasCtrlDep=1, hasSideEffects=1 in
+def ERet : PseudoSE<(outs), (ins), [(MipsERet)]>;
 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
 [(callseq_start timm:$amt)]>;
 def ADJCALLSTACKUP   : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
 def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
 ISA_MIPS2;
 }
 }
-def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
+def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
-def SYNCI : MMRel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
+def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
 let AdditionalPredicates = [NotInMicroMips] in {
 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2;
 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2;
 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>, ISA_MIPS2;
 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
 def TRAP : TrapBase<BREAK>;
 def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
 let AdditionalPredicates = [NotInMicroMips] in {
 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18, 0x0>, INSN_MIPS3_32;
 def ERETNC : MMRel, ER_FT<"eretnc">, ER_FM<0x18, 0x1>, ISA_MIPS32R5;
-}
+def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f, 0x0>, ISA_MIPS32;
-def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f, 0x0>, ISA_MIPS32;
+}
 let AdditionalPredicates = [NotInMicroMips] in {
 def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
-}
+def DI : MMRel, StdMMR6Rel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
-def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
+}
 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
 AdditionalPredicates = [NotInMicroMips] in {
 def WAIT : WAIT_FT<"wait">, WAIT_FM;
 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
+let AdditionalPredicates = [NotInMicroMips] in {
 def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
+}
-def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
+// TODO: Add '0 < pos+size <= 32' constraint check to ext instruction
+def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, MipsExt>,
+EXT_FM<0>;
 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
 /// Move Control Registers From/To CPU Registers
 def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
 def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
 def MFC2 : MFC3OP<"mfc2", GPR32Opnd, COP2Opnd>, MFC3OP_FM<0x12, 0>;
 def MTC2 : MTC3OP<"mtc2", COP2Opnd, GPR32Opnd>, MFC3OP_FM<0x12, 4>;
 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
 FrmOther, asmstr>;
-def SSNOP : MMRel, Barrier<"ssnop">, BARRIER_FM<1>;
+def SSNOP : MMRel, StdMMR6Rel, Barrier<"ssnop">, BARRIER_FM<1>;
 def EHB : MMRel, Barrier<"ehb">, BARRIER_FM<3>;
-def PAUSE : MMRel, Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
+def PAUSE : MMRel, StdMMR6Rel, Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
 // JR_HB and JALR_HB are defined here using the new style naming
 // scheme because some of this code is shared with Mips32r6InstrInfo.td
 // and because of that it doesn't follow the naming convention of the
 // rest of the file. To avoid a mixture of old vs new style, the new
 def CACHE : MMRel, CacheOp<"cache", mem>, CACHEOP_FM<0b101111>,
 INSN_MIPS3_32_NOT_32R6_64R6;
 def PREF :  MMRel, CacheOp<"pref", mem>, CACHEOP_FM<0b110011>,
 INSN_MIPS3_32_NOT_32R6_64R6;
+def ROL : MipsAsmPseudoInst<(outs),
+(ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd),
+"rol\t$rs, $rt, $rd">;
+def ROLImm : MipsAsmPseudoInst<(outs),
+(ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
+"rol\t$rs, $rt, $imm">;
+def : MipsInstAlias<"rol $rd, $rs",
+(ROL GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
+def : MipsInstAlias<"rol $rd, $imm",
+(ROLImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>;
+def ROR : MipsAsmPseudoInst<(outs),
+(ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd),
+"ror\t$rs, $rt, $rd">;
+def RORImm : MipsAsmPseudoInst<(outs),
+(ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
+"ror\t$rs, $rt, $imm">;
+def : MipsInstAlias<"ror $rd, $rs",
+(ROR GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
+def : MipsInstAlias<"ror $rd, $imm",
+(RORImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>;
+def DROL : MipsAsmPseudoInst<(outs),
+(ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd),
+"drol\t$rs, $rt, $rd">, ISA_MIPS64;
+def DROLImm : MipsAsmPseudoInst<(outs),
+(ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
+"drol\t$rs, $rt, $imm">, ISA_MIPS64;
+def : MipsInstAlias<"drol $rd, $rs",
+(DROL GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>, ISA_MIPS64;
+def : MipsInstAlias<"drol $rd, $imm",
+(DROLImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>, ISA_MIPS64;
+def DROR : MipsAsmPseudoInst<(outs),
+(ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd),
+"dror\t$rs, $rt, $rd">, ISA_MIPS64;
+def DRORImm : MipsAsmPseudoInst<(outs),
+(ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
+"dror\t$rs, $rt, $imm">, ISA_MIPS64;
+def : MipsInstAlias<"dror $rd, $rs",
+(DROR GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>, ISA_MIPS64;
+def : MipsInstAlias<"dror $rd, $imm",
+(DRORImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>, ISA_MIPS64;
 //===----------------------------------------------------------------------===//
 // Instruction aliases
 //===----------------------------------------------------------------------===//
 def : MipsInstAlias<"move $dst, $src",
 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
 let AdditionalPredicates = [NotInMicroMips] in {
 def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2;
-}
+def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;
-def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;
+}
 let AdditionalPredicates = [NotInMicroMips] in {
 def : MipsInstAlias<"teq $rs, $rt",
 (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
 def : MipsInstAlias<"tge $rs, $rt",
 (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
 //===----------------------------------------------------------------------===//
 class LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> :
 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
 !strconcat(instr_asm, "\t$rt, $imm32")> ;
-def LoadImm32 : LoadImmediate32<"li", uimm5, GPR32Opnd>;
+def LoadImm32 : LoadImmediate32<"li", simm32, GPR32Opnd>;
 class LoadAddressFromReg32<string instr_asm, Operand MemOpnd,
 RegisterOperand RO> :
 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
 !strconcat(instr_asm, "\t$rt, $addr")> ;
 def LoadAddrReg32 : LoadAddressFromReg32<"la", mem, GPR32Opnd>;
 class LoadAddressFromImm32<string instr_asm, Operand Od, RegisterOperand RO> :
 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
 !strconcat(instr_asm, "\t$rt, $imm32")> ;
-def LoadAddrImm32 : LoadAddressFromImm32<"la", uimm5, GPR32Opnd>;
+def LoadAddrImm32 : LoadAddressFromImm32<"la", simm32, GPR32Opnd>;
 def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
 "jal\t$rd, $rs"> ;
 def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs),
 "jal\t$rs"> ;
 "ddiv\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
 def DUDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
 "ddivu\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
+def Ulh : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
+"ulh\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
 def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
 "ulhu\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
 def Ulw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
 "ulw\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
 // SYNC
 def : MipsPat<(MipsSync (i32 immz)),
 (SYNC 0)>, ISA_MIPS2;
 // Call
-def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
-(JAL tglobaladdr:$dst)>;
 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
 (JAL texternalsym:$dst)>;
 //def : MipsPat<(MipsJmpLink GPR32:$dst),
 //              (JALR GPR32:$dst)>;
 let AdditionalPredicates = [NotInMicroMips] in {
 def : LoadRegImmPat<LW, i32, load>;
 }
 }
+// Atomic load patterns.
+def : MipsPat<(atomic_load_8 addr:$a), (LB addr:$a)>;
+def : MipsPat<(atomic_load_16 addr:$a), (LH addr:$a)>;
+def : MipsPat<(atomic_load_32 addr:$a), (LW addr:$a)>;
+// Atomic store patterns.
+def : MipsPat<(atomic_store_8 addr:$a, GPR32:$v), (SB GPR32:$v, addr:$a)>;
+def : MipsPat<(atomic_store_16 addr:$a, GPR32:$v), (SH GPR32:$v, addr:$a)>;
+def : MipsPat<(atomic_store_32 addr:$a, GPR32:$v), (SW GPR32:$v, addr:$a)>;
 //===----------------------------------------------------------------------===//
 // Floating Point Support
 //===----------------------------------------------------------------------===//
 include "MipsInstrFPU.td"

Mercurial > hg > CbC > CbC_llvm

comparison lib/Target/Mips/MipsInstrInfo.td @ 100:7d135dc70f03 LLVM 3.9