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comparison test/CodeGen/AArch64/arm64-swizzle-tbl-i16-layout.ll @ 100:7d135dc70f03 LLVM 3.9

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents 54457678186b
children
comparison
equal deleted inserted replaced
96:6418606d0ead 100:7d135dc70f03
2 ; rdar://13214163 - Make sure we generate a correct lookup table for the TBL 2 ; rdar://13214163 - Make sure we generate a correct lookup table for the TBL
3 ; instruction when the element size of the vector is not 8 bits. We were 3 ; instruction when the element size of the vector is not 8 bits. We were
4 ; getting both the endianness wrong and the element indexing wrong. 4 ; getting both the endianness wrong and the element indexing wrong.
5 define <8 x i16> @foo(<8 x i16> %a) nounwind readnone { 5 define <8 x i16> @foo(<8 x i16> %a) nounwind readnone {
6 ; CHECK: .section __TEXT,__literal16,16byte_literals 6 ; CHECK: .section __TEXT,__literal16,16byte_literals
7 ; CHECK: .align 4 7 ; CHECK: .p2align 4
8 ; CHECK:lCPI0_0: 8 ; CHECK:lCPI0_0:
9 ; CHECK: .byte 0 ; 0x0 9 ; CHECK: .byte 0 ; 0x0
10 ; CHECK: .byte 1 ; 0x1 10 ; CHECK: .byte 1 ; 0x1
11 ; CHECK: .byte 0 ; 0x0 11 ; CHECK: .byte 0 ; 0x0
12 ; CHECK: .byte 1 ; 0x1 12 ; CHECK: .byte 1 ; 0x1
22 ; CHECK: .byte 9 ; 0x9 22 ; CHECK: .byte 9 ; 0x9
23 ; CHECK: .byte 8 ; 0x8 23 ; CHECK: .byte 8 ; 0x8
24 ; CHECK: .byte 9 ; 0x9 24 ; CHECK: .byte 9 ; 0x9
25 ; CHECK: .section __TEXT,__text,regular,pure_instructions 25 ; CHECK: .section __TEXT,__text,regular,pure_instructions
26 ; CHECK: .globl _foo 26 ; CHECK: .globl _foo
27 ; CHECK: .align 2 27 ; CHECK: .p2align 2
28 ; CHECK:_foo: ; @foo 28 ; CHECK:_foo: ; @foo
29 ; CHECK: adrp [[BASE:x[0-9]+]], lCPI0_0@PAGE 29 ; CHECK: adrp [[BASE:x[0-9]+]], lCPI0_0@PAGE
30 ; CHECK: ldr q[[REG:[0-9]+]], {{\[}}[[BASE]], lCPI0_0@PAGEOFF] 30 ; CHECK: ldr q[[REG:[0-9]+]], {{\[}}[[BASE]], lCPI0_0@PAGEOFF]
31 ; CHECK: tbl.16b v0, { v0 }, v[[REG]] 31 ; CHECK: tbl.16b v0, { v0 }, v[[REG]]
32 ; CHECK: ret 32 ; CHECK: ret