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comparison test/CodeGen/AArch64/bitfield-insert.ll @ 100:7d135dc70f03 LLVM 3.9

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children 1172e4bd9c6f
comparison
equal deleted inserted replaced
96:6418606d0ead 100:7d135dc70f03
213 ; CHECK: and [[BIT:w[0-9]+]], {{w[0-9]+}}, #0xffff 213 ; CHECK: and [[BIT:w[0-9]+]], {{w[0-9]+}}, #0xffff
214 ; CHECK: bfi [[BIT]], {{w[0-9]+}}, #16, #8 214 ; CHECK: bfi [[BIT]], {{w[0-9]+}}, #16, #8
215 215
216 ret void 216 ret void
217 } 217 }
218
219 ; Tests when all the bits from one operand are not useful
220 define i32 @test_nouseful_bits(i8 %a, i32 %b) {
221 ; CHECK-LABEL: test_nouseful_bits:
222 ; CHECK: bfi
223 ; CHECK: bfi
224 ; CHECK: bfi
225 ; CHECK-NOT: bfi
226 ; CHECK-NOT: or
227 ; CHECK: lsl
228 %conv = zext i8 %a to i32 ; 0 0 0 A
229 %shl = shl i32 %b, 8 ; B2 B1 B0 0
230 %or = or i32 %conv, %shl ; B2 B1 B0 A
231 %shl.1 = shl i32 %or, 8 ; B1 B0 A 0
232 %or.1 = or i32 %conv, %shl.1 ; B1 B0 A A
233 %shl.2 = shl i32 %or.1, 8 ; B0 A A 0
234 %or.2 = or i32 %conv, %shl.2 ; B0 A A A
235 %shl.3 = shl i32 %or.2, 8 ; A A A 0
236 %or.3 = or i32 %conv, %shl.3 ; A A A A
237 %shl.4 = shl i32 %or.3, 8 ; A A A 0
238 ret i32 %shl.4
239 }