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comparison test/CodeGen/AMDGPU/fneg-fabs.ll @ 100:7d135dc70f03 LLVM 3.9

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children 1172e4bd9c6f
comparison
equal deleted inserted replaced
96:6418606d0ead 100:7d135dc70f03
32 ; FUNC-LABEL: {{^}}fneg_fabs_free_f32: 32 ; FUNC-LABEL: {{^}}fneg_fabs_free_f32:
33 ; R600-NOT: AND 33 ; R600-NOT: AND
34 ; R600: |PV.{{[XYZW]}}| 34 ; R600: |PV.{{[XYZW]}}|
35 ; R600: -PV 35 ; R600: -PV
36 36
37 ; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000 37 ; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
38 ; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
39 define void @fneg_fabs_free_f32(float addrspace(1)* %out, i32 %in) { 38 define void @fneg_fabs_free_f32(float addrspace(1)* %out, i32 %in) {
40 %bc = bitcast i32 %in to float 39 %bc = bitcast i32 %in to float
41 %fabs = call float @llvm.fabs.f32(float %bc) 40 %fabs = call float @llvm.fabs.f32(float %bc)
42 %fsub = fsub float -0.000000e+00, %fabs 41 %fsub = fsub float -0.000000e+00, %fabs
43 store float %fsub, float addrspace(1)* %out 42 store float %fsub, float addrspace(1)* %out
47 ; FUNC-LABEL: {{^}}fneg_fabs_fn_free_f32: 46 ; FUNC-LABEL: {{^}}fneg_fabs_fn_free_f32:
48 ; R600-NOT: AND 47 ; R600-NOT: AND
49 ; R600: |PV.{{[XYZW]}}| 48 ; R600: |PV.{{[XYZW]}}|
50 ; R600: -PV 49 ; R600: -PV
51 50
52 ; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000 51 ; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
53 ; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
54 define void @fneg_fabs_fn_free_f32(float addrspace(1)* %out, i32 %in) { 52 define void @fneg_fabs_fn_free_f32(float addrspace(1)* %out, i32 %in) {
55 %bc = bitcast i32 %in to float 53 %bc = bitcast i32 %in to float
56 %fabs = call float @fabs(float %bc) 54 %fabs = call float @fabs(float %bc)
57 %fsub = fsub float -0.000000e+00, %fabs 55 %fsub = fsub float -0.000000e+00, %fabs
58 store float %fsub, float addrspace(1)* %out 56 store float %fsub, float addrspace(1)* %out
59 ret void 57 ret void
60 } 58 }
61 59
62 ; FUNC-LABEL: {{^}}fneg_fabs_f32: 60 ; FUNC-LABEL: {{^}}fneg_fabs_f32:
63 ; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000 61 ; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
64 ; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
65 define void @fneg_fabs_f32(float addrspace(1)* %out, float %in) { 62 define void @fneg_fabs_f32(float addrspace(1)* %out, float %in) {
66 %fabs = call float @llvm.fabs.f32(float %in) 63 %fabs = call float @llvm.fabs.f32(float %in)
67 %fsub = fsub float -0.000000e+00, %fabs 64 %fsub = fsub float -0.000000e+00, %fabs
68 store float %fsub, float addrspace(1)* %out, align 4 65 store float %fsub, float addrspace(1)* %out, align 4
69 ret void 66 ret void
83 ; R600: |{{(PV|T[0-9])\.[XYZW]}}| 80 ; R600: |{{(PV|T[0-9])\.[XYZW]}}|
84 ; R600: -PV 81 ; R600: -PV
85 ; R600: |{{(PV|T[0-9])\.[XYZW]}}| 82 ; R600: |{{(PV|T[0-9])\.[XYZW]}}|
86 ; R600: -PV 83 ; R600: -PV
87 84
88 ; FIXME: SGPR should be used directly for first src operand. 85 ; SI: v_or_b32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
89 ; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000 86 ; SI: v_or_b32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
90 ; SI-NOT: 0x80000000
91 ; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
92 ; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
93 define void @fneg_fabs_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) { 87 define void @fneg_fabs_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) {
94 %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in) 88 %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in)
95 %fsub = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %fabs 89 %fsub = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %fabs
96 store <2 x float> %fsub, <2 x float> addrspace(1)* %out 90 store <2 x float> %fsub, <2 x float> addrspace(1)* %out
97 ret void 91 ret void
98 } 92 }
99 93
100 ; FIXME: SGPR should be used directly for first src operand.
101 ; FUNC-LABEL: {{^}}fneg_fabs_v4f32: 94 ; FUNC-LABEL: {{^}}fneg_fabs_v4f32:
102 ; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000 95 ; SI: v_or_b32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
103 ; SI-NOT: 0x80000000 96 ; SI: v_or_b32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
104 ; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]] 97 ; SI: v_or_b32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
105 ; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]] 98 ; SI: v_or_b32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
106 ; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
107 ; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
108 define void @fneg_fabs_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) { 99 define void @fneg_fabs_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) {
109 %fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in) 100 %fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in)
110 %fsub = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %fabs 101 %fsub = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %fabs
111 store <4 x float> %fsub, <4 x float> addrspace(1)* %out 102 store <4 x float> %fsub, <4 x float> addrspace(1)* %out
112 ret void 103 ret void