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comparison test/CodeGen/AMDGPU/llvm.amdgcn.read.workdim.ll @ 100:7d135dc70f03 LLVM 3.9

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
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96:6418606d0ead 100:7d135dc70f03
1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=SI-NOHSA -check-prefix=GCN-NOHSA %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOHSA -check-prefix=GCN -check-prefix=GCN-NOHSA %s
3
4 ; GCN-LABEL: {{^}}read_workdim:
5 ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xb
6 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2c
7 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
8 ; GCN-NOHSA: buffer_store_dword [[VVAL]]
9 define void @read_workdim(i32 addrspace(1)* %out) {
10 entry:
11 %0 = call i32 @llvm.amdgcn.read.workdim() #0
12 store i32 %0, i32 addrspace(1)* %out
13 ret void
14 }
15
16 ; GCN-LABEL: {{^}}read_workdim_known_bits:
17 ; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xb
18 ; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2c
19 ; GCN-NOT: 0xff
20 ; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
21 ; GCN: buffer_store_dword [[VVAL]]
22 define void @read_workdim_known_bits(i32 addrspace(1)* %out) {
23 entry:
24 %dim = call i32 @llvm.amdgcn.read.workdim() #0
25 %shl = shl i32 %dim, 24
26 %shr = lshr i32 %shl, 24
27 store i32 %shr, i32 addrspace(1)* %out
28 ret void
29 }
30
31 ; GCN-LABEL: {{^}}legacy_read_workdim:
32 ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xb
33 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2c
34 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
35 ; GCN-NOHSA: buffer_store_dword [[VVAL]]
36 define void @legacy_read_workdim(i32 addrspace(1)* %out) {
37 entry:
38 %dim = call i32 @llvm.AMDGPU.read.workdim() #0
39 store i32 %dim, i32 addrspace(1)* %out
40 ret void
41 }
42
43 declare i32 @llvm.amdgcn.read.workdim() #0
44 declare i32 @llvm.AMDGPU.read.workdim() #0
45
46 attributes #0 = { nounwind readnone }