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comparison test/CodeGen/X86/avx512cdvl-intrinsics.ll @ 100:7d135dc70f03 LLVM 3.9

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children 803732b1fca8
comparison
equal deleted inserted replaced
96:6418606d0ead 100:7d135dc70f03
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512cd -mattr=+avx512vl| FileCheck %s 2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512cd -mattr=+avx512vl| FileCheck %s
2 3
3 declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) nounwind readonly 4 declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) nounwind readonly
4 5
5 declare <4 x i32> @llvm.x86.avx512.mask.lzcnt.d.128(<4 x i32>, <4 x i32>, i8) 6 declare <4 x i32> @llvm.x86.avx512.mask.lzcnt.d.128(<4 x i32>, <4 x i32>, i8)
6 7
7 define <4 x i32>@test_int_x86_avx512_mask_vplzcnt_d_128(<4 x i32> %x0, <4 x i32> %x1, i8 %x2) { 8 define <4 x i32>@test_int_x86_avx512_mask_vplzcnt_d_128(<4 x i32> %x0, <4 x i32> %x1, i8 %x2) {
8 ; CHECK-LABEL: test_int_x86_avx512_mask_vplzcnt_d_128: 9 ; CHECK-LABEL: test_int_x86_avx512_mask_vplzcnt_d_128:
9 ; CHECK: ## BB#0: 10 ; CHECK: ## BB#0:
10 ; CHECK-NEXT: movzbl %dil, %eax 11 ; CHECK-NEXT: kmovw %edi, %k1
11 ; CHECK-NEXT: kmovw %eax, %k1
12 ; CHECK-NEXT: vplzcntd %xmm0, %xmm1 {%k1} 12 ; CHECK-NEXT: vplzcntd %xmm0, %xmm1 {%k1}
13 ; CHECK-NEXT: vplzcntd %xmm0, %xmm2 {%k1} {z} 13 ; CHECK-NEXT: vplzcntd %xmm0, %xmm2 {%k1} {z}
14 ; CHECK-NEXT: vplzcntd %xmm0, %xmm0 14 ; CHECK-NEXT: vplzcntd %xmm0, %xmm0
15 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 15 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
16 ; CHECK-NEXT: vpaddd %xmm2, %xmm0, %xmm0 16 ; CHECK-NEXT: vpaddd %xmm2, %xmm0, %xmm0
26 declare <8 x i32> @llvm.x86.avx512.mask.lzcnt.d.256(<8 x i32>, <8 x i32>, i8) 26 declare <8 x i32> @llvm.x86.avx512.mask.lzcnt.d.256(<8 x i32>, <8 x i32>, i8)
27 27
28 define <8 x i32>@test_int_x86_avx512_mask_vplzcnt_d_256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2) { 28 define <8 x i32>@test_int_x86_avx512_mask_vplzcnt_d_256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2) {
29 ; CHECK-LABEL: test_int_x86_avx512_mask_vplzcnt_d_256: 29 ; CHECK-LABEL: test_int_x86_avx512_mask_vplzcnt_d_256:
30 ; CHECK: ## BB#0: 30 ; CHECK: ## BB#0:
31 ; CHECK-NEXT: movzbl %dil, %eax 31 ; CHECK-NEXT: kmovw %edi, %k1
32 ; CHECK-NEXT: kmovw %eax, %k1
33 ; CHECK-NEXT: vplzcntd %ymm0, %ymm1 {%k1} 32 ; CHECK-NEXT: vplzcntd %ymm0, %ymm1 {%k1}
34 ; CHECK-NEXT: vplzcntd %ymm0, %ymm0 33 ; CHECK-NEXT: vplzcntd %ymm0, %ymm0
35 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 34 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
36 ; CHECK-NEXT: retq 35 ; CHECK-NEXT: retq
37 %res = call <8 x i32> @llvm.x86.avx512.mask.lzcnt.d.256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2) 36 %res = call <8 x i32> @llvm.x86.avx512.mask.lzcnt.d.256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2)
43 declare <2 x i64> @llvm.x86.avx512.mask.lzcnt.q.128(<2 x i64>, <2 x i64>, i8) 42 declare <2 x i64> @llvm.x86.avx512.mask.lzcnt.q.128(<2 x i64>, <2 x i64>, i8)
44 43
45 define <2 x i64>@test_int_x86_avx512_mask_vplzcnt_q_128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2) { 44 define <2 x i64>@test_int_x86_avx512_mask_vplzcnt_q_128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2) {
46 ; CHECK-LABEL: test_int_x86_avx512_mask_vplzcnt_q_128: 45 ; CHECK-LABEL: test_int_x86_avx512_mask_vplzcnt_q_128:
47 ; CHECK: ## BB#0: 46 ; CHECK: ## BB#0:
48 ; CHECK-NEXT: movzbl %dil, %eax 47 ; CHECK-NEXT: kmovw %edi, %k1
49 ; CHECK-NEXT: kmovw %eax, %k1
50 ; CHECK-NEXT: vplzcntq %xmm0, %xmm1 {%k1} 48 ; CHECK-NEXT: vplzcntq %xmm0, %xmm1 {%k1}
51 ; CHECK-NEXT: vplzcntq %xmm0, %xmm0 49 ; CHECK-NEXT: vplzcntq %xmm0, %xmm0
52 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0 50 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
53 ; CHECK-NEXT: retq 51 ; CHECK-NEXT: retq
54 %res = call <2 x i64> @llvm.x86.avx512.mask.lzcnt.q.128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2) 52 %res = call <2 x i64> @llvm.x86.avx512.mask.lzcnt.q.128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2)
60 declare <4 x i64> @llvm.x86.avx512.mask.lzcnt.q.256(<4 x i64>, <4 x i64>, i8) 58 declare <4 x i64> @llvm.x86.avx512.mask.lzcnt.q.256(<4 x i64>, <4 x i64>, i8)
61 59
62 define <4 x i64>@test_int_x86_avx512_mask_vplzcnt_q_256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2) { 60 define <4 x i64>@test_int_x86_avx512_mask_vplzcnt_q_256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2) {
63 ; CHECK-LABEL: test_int_x86_avx512_mask_vplzcnt_q_256: 61 ; CHECK-LABEL: test_int_x86_avx512_mask_vplzcnt_q_256:
64 ; CHECK: ## BB#0: 62 ; CHECK: ## BB#0:
65 ; CHECK-NEXT: movzbl %dil, %eax 63 ; CHECK-NEXT: kmovw %edi, %k1
66 ; CHECK-NEXT: kmovw %eax, %k1
67 ; CHECK-NEXT: vplzcntq %ymm0, %ymm1 {%k1} 64 ; CHECK-NEXT: vplzcntq %ymm0, %ymm1 {%k1}
68 ; CHECK-NEXT: vplzcntq %ymm0, %ymm0 65 ; CHECK-NEXT: vplzcntq %ymm0, %ymm0
69 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0 66 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
70 ; CHECK-NEXT: retq 67 ; CHECK-NEXT: retq
71 %res = call <4 x i64> @llvm.x86.avx512.mask.lzcnt.q.256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2) 68 %res = call <4 x i64> @llvm.x86.avx512.mask.lzcnt.q.256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2)
77 declare <4 x i32> @llvm.x86.avx512.mask.conflict.d.128(<4 x i32>, <4 x i32>, i8) 74 declare <4 x i32> @llvm.x86.avx512.mask.conflict.d.128(<4 x i32>, <4 x i32>, i8)
78 75
79 define <4 x i32>@test_int_x86_avx512_mask_vpconflict_d_128(<4 x i32> %x0, <4 x i32> %x1, i8 %x2) { 76 define <4 x i32>@test_int_x86_avx512_mask_vpconflict_d_128(<4 x i32> %x0, <4 x i32> %x1, i8 %x2) {
80 ; CHECK-LABEL: test_int_x86_avx512_mask_vpconflict_d_128: 77 ; CHECK-LABEL: test_int_x86_avx512_mask_vpconflict_d_128:
81 ; CHECK: ## BB#0: 78 ; CHECK: ## BB#0:
82 ; CHECK-NEXT: movzbl %dil, %eax 79 ; CHECK-NEXT: kmovw %edi, %k1
83 ; CHECK-NEXT: kmovw %eax, %k1
84 ; CHECK-NEXT: vpconflictd %xmm0, %xmm1 {%k1} 80 ; CHECK-NEXT: vpconflictd %xmm0, %xmm1 {%k1}
85 ; CHECK-NEXT: vpconflictd %xmm0, %xmm2 {%k1} {z} 81 ; CHECK-NEXT: vpconflictd %xmm0, %xmm2 {%k1} {z}
86 ; CHECK-NEXT: vpconflictd %xmm0, %xmm0 82 ; CHECK-NEXT: vpconflictd %xmm0, %xmm0
87 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 83 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
88 ; CHECK-NEXT: vpaddd %xmm2, %xmm0, %xmm0 84 ; CHECK-NEXT: vpaddd %xmm2, %xmm0, %xmm0
98 declare <8 x i32> @llvm.x86.avx512.mask.conflict.d.256(<8 x i32>, <8 x i32>, i8) 94 declare <8 x i32> @llvm.x86.avx512.mask.conflict.d.256(<8 x i32>, <8 x i32>, i8)
99 95
100 define <8 x i32>@test_int_x86_avx512_mask_vpconflict_d_256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2) { 96 define <8 x i32>@test_int_x86_avx512_mask_vpconflict_d_256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2) {
101 ; CHECK-LABEL: test_int_x86_avx512_mask_vpconflict_d_256: 97 ; CHECK-LABEL: test_int_x86_avx512_mask_vpconflict_d_256:
102 ; CHECK: ## BB#0: 98 ; CHECK: ## BB#0:
103 ; CHECK-NEXT: movzbl %dil, %eax 99 ; CHECK-NEXT: kmovw %edi, %k1
104 ; CHECK-NEXT: kmovw %eax, %k1
105 ; CHECK-NEXT: vpconflictd %ymm0, %ymm1 {%k1} 100 ; CHECK-NEXT: vpconflictd %ymm0, %ymm1 {%k1}
106 ; CHECK-NEXT: vpconflictd %ymm0, %ymm0 101 ; CHECK-NEXT: vpconflictd %ymm0, %ymm0
107 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 102 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
108 ; CHECK-NEXT: retq 103 ; CHECK-NEXT: retq
109 %res = call <8 x i32> @llvm.x86.avx512.mask.conflict.d.256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2) 104 %res = call <8 x i32> @llvm.x86.avx512.mask.conflict.d.256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2)
115 declare <2 x i64> @llvm.x86.avx512.mask.conflict.q.128(<2 x i64>, <2 x i64>, i8) 110 declare <2 x i64> @llvm.x86.avx512.mask.conflict.q.128(<2 x i64>, <2 x i64>, i8)
116 111
117 define <2 x i64>@test_int_x86_avx512_mask_vpconflict_q_128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2) { 112 define <2 x i64>@test_int_x86_avx512_mask_vpconflict_q_128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2) {
118 ; CHECK-LABEL: test_int_x86_avx512_mask_vpconflict_q_128: 113 ; CHECK-LABEL: test_int_x86_avx512_mask_vpconflict_q_128:
119 ; CHECK: ## BB#0: 114 ; CHECK: ## BB#0:
120 ; CHECK-NEXT: movzbl %dil, %eax 115 ; CHECK-NEXT: kmovw %edi, %k1
121 ; CHECK-NEXT: kmovw %eax, %k1
122 ; CHECK-NEXT: vpconflictq %xmm0, %xmm1 {%k1} 116 ; CHECK-NEXT: vpconflictq %xmm0, %xmm1 {%k1}
123 ; CHECK-NEXT: vpconflictq %xmm0, %xmm0 117 ; CHECK-NEXT: vpconflictq %xmm0, %xmm0
124 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0 118 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
125 ; CHECK-NEXT: retq 119 ; CHECK-NEXT: retq
126 %res = call <2 x i64> @llvm.x86.avx512.mask.conflict.q.128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2) 120 %res = call <2 x i64> @llvm.x86.avx512.mask.conflict.q.128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2)
132 declare <4 x i64> @llvm.x86.avx512.mask.conflict.q.256(<4 x i64>, <4 x i64>, i8) 126 declare <4 x i64> @llvm.x86.avx512.mask.conflict.q.256(<4 x i64>, <4 x i64>, i8)
133 127
134 define <4 x i64>@test_int_x86_avx512_mask_vpconflict_q_256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2) { 128 define <4 x i64>@test_int_x86_avx512_mask_vpconflict_q_256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2) {
135 ; CHECK-LABEL: test_int_x86_avx512_mask_vpconflict_q_256: 129 ; CHECK-LABEL: test_int_x86_avx512_mask_vpconflict_q_256:
136 ; CHECK: ## BB#0: 130 ; CHECK: ## BB#0:
137 ; CHECK-NEXT: movzbl %dil, %eax 131 ; CHECK-NEXT: kmovw %edi, %k1
138 ; CHECK-NEXT: kmovw %eax, %k1
139 ; CHECK-NEXT: vpconflictq %ymm0, %ymm1 {%k1} 132 ; CHECK-NEXT: vpconflictq %ymm0, %ymm1 {%k1}
140 ; CHECK-NEXT: vpconflictq %ymm0, %ymm0 133 ; CHECK-NEXT: vpconflictq %ymm0, %ymm0
141 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0 134 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
142 ; CHECK-NEXT: retq 135 ; CHECK-NEXT: retq
143 %res = call <4 x i64> @llvm.x86.avx512.mask.conflict.q.256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2) 136 %res = call <4 x i64> @llvm.x86.avx512.mask.conflict.q.256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2)
144 %res1 = call <4 x i64> @llvm.x86.avx512.mask.conflict.q.256(<4 x i64> %x0, <4 x i64> %x1, i8 -1) 137 %res1 = call <4 x i64> @llvm.x86.avx512.mask.conflict.q.256(<4 x i64> %x0, <4 x i64> %x1, i8 -1)
145 %res2 = add <4 x i64> %res, %res1 138 %res2 = add <4 x i64> %res, %res1
146 ret <4 x i64> %res2 139 ret <4 x i64> %res2
147 } 140 }
148 141
142 define <8 x i32> @test_x86_vbroadcastmw_256(i16 %a0) {
143 ; CHECK-LABEL: test_x86_vbroadcastmw_256:
144 ; CHECK: ## BB#0:
145 ; CHECK-NEXT: kmovw %edi, %k0
146 ; CHECK-NEXT: vpbroadcastmw2d %k0, %ymm0
147 ; CHECK-NEXT: retq
148 %res = call <8 x i32> @llvm.x86.avx512.broadcastmw.256(i16 %a0) ;
149 ret <8 x i32> %res
150 }
151 declare <8 x i32> @llvm.x86.avx512.broadcastmw.256(i16)
152
153 define <4 x i32> @test_x86_vbroadcastmw_128(i16 %a0) {
154 ; CHECK-LABEL: test_x86_vbroadcastmw_128:
155 ; CHECK: ## BB#0:
156 ; CHECK-NEXT: kmovw %edi, %k0
157 ; CHECK-NEXT: vpbroadcastmw2d %k0, %xmm0
158 ; CHECK-NEXT: retq
159 %res = call <4 x i32> @llvm.x86.avx512.broadcastmw.128(i16 %a0) ;
160 ret <4 x i32> %res
161 }
162 declare <4 x i32> @llvm.x86.avx512.broadcastmw.128(i16)
163
164 define <4 x i64> @test_x86_broadcastmb_256(i8 %a0) {
165 ; CHECK-LABEL: test_x86_broadcastmb_256:
166 ; CHECK: ## BB#0:
167 ; CHECK-NEXT: kmovw %edi, %k0
168 ; CHECK-NEXT: vpbroadcastmb2q %k0, %ymm0
169 ; CHECK-NEXT: retq
170 %res = call <4 x i64> @llvm.x86.avx512.broadcastmb.256(i8 %a0) ;
171 ret <4 x i64> %res
172 }
173 declare <4 x i64> @llvm.x86.avx512.broadcastmb.256(i8)
174
175 define <2 x i64> @test_x86_broadcastmb_128(i8 %a0) {
176 ; CHECK-LABEL: test_x86_broadcastmb_128:
177 ; CHECK: ## BB#0:
178 ; CHECK-NEXT: kmovw %edi, %k0
179 ; CHECK-NEXT: vpbroadcastmb2q %k0, %xmm0
180 ; CHECK-NEXT: retq
181 %res = call <2 x i64> @llvm.x86.avx512.broadcastmb.128(i8 %a0) ;
182 ret <2 x i64> %res
183 }
184 declare <2 x i64> @llvm.x86.avx512.broadcastmb.128(i8)