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comparison test/Transforms/InstCombine/store.ll @ 100:7d135dc70f03 LLVM 3.9

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children 3a76565eade5
comparison
equal deleted inserted replaced
96:6418606d0ead 100:7d135dc70f03
111 ; CHECK: for.cond: 111 ; CHECK: for.cond:
112 ; CHECK-NEXT: phi i32 [ 42 112 ; CHECK-NEXT: phi i32 [ 42
113 ; CHECK-NEXT: store i32 %storemerge, i32* %gi, align 4, !tbaa !0 113 ; CHECK-NEXT: store i32 %storemerge, i32* %gi, align 4, !tbaa !0
114 } 114 }
115 115
116 define void @dse1(i32* %p) {
117 ; CHECK-LABEL: dse1
118 ; CHECK-NEXT: store
119 ; CHECK-NEXT: ret
120 store i32 0, i32* %p
121 store i32 0, i32* %p
122 ret void
123 }
124
125 ; Slightly subtle: if we're mixing atomic and non-atomic access to the
126 ; same location, then the contents of the location are undefined if there's
127 ; an actual race. As such, we're free to pick either store under the
128 ; assumption that we're not racing with any other thread.
129 define void @dse2(i32* %p) {
130 ; CHECK-LABEL: dse2
131 ; CHECK-NEXT: store i32 0, i32* %p
132 ; CHECK-NEXT: ret
133 store atomic i32 0, i32* %p unordered, align 4
134 store i32 0, i32* %p
135 ret void
136 }
137
138 define void @dse3(i32* %p) {
139 ; CHECK-LABEL: dse3
140 ; CHECK-NEXT: store atomic i32 0, i32* %p unordered, align 4
141 ; CHECK-NEXT: ret
142 store i32 0, i32* %p
143 store atomic i32 0, i32* %p unordered, align 4
144 ret void
145 }
146
147 define void @dse4(i32* %p) {
148 ; CHECK-LABEL: dse4
149 ; CHECK-NEXT: store atomic i32 0, i32* %p unordered, align 4
150 ; CHECK-NEXT: ret
151 store atomic i32 0, i32* %p unordered, align 4
152 store atomic i32 0, i32* %p unordered, align 4
153 ret void
154 }
155
156 ; Implementation limit - could remove unordered store here, but
157 ; currently don't.
158 define void @dse5(i32* %p) {
159 ; CHECK-LABEL: dse5
160 ; CHECK-NEXT: store
161 ; CHECK-NEXT: store
162 ; CHECK-NEXT: ret
163 store atomic i32 0, i32* %p unordered, align 4
164 store atomic i32 0, i32* %p seq_cst, align 4
165 ret void
166 }
167
168 define void @write_back1(i32* %p) {
169 ; CHECK-LABEL: write_back1
170 ; CHECK-NEXT: ret
171 %v = load i32, i32* %p
172 store i32 %v, i32* %p
173 ret void
174 }
175
176 define void @write_back2(i32* %p) {
177 ; CHECK-LABEL: write_back2
178 ; CHECK-NEXT: ret
179 %v = load atomic i32, i32* %p unordered, align 4
180 store i32 %v, i32* %p
181 ret void
182 }
183
184 define void @write_back3(i32* %p) {
185 ; CHECK-LABEL: write_back3
186 ; CHECK-NEXT: ret
187 %v = load i32, i32* %p
188 store atomic i32 %v, i32* %p unordered, align 4
189 ret void
190 }
191
192 define void @write_back4(i32* %p) {
193 ; CHECK-LABEL: write_back4
194 ; CHECK-NEXT: ret
195 %v = load atomic i32, i32* %p unordered, align 4
196 store atomic i32 %v, i32* %p unordered, align 4
197 ret void
198 }
199
200 ; Can't remove store due to ordering side effect
201 define void @write_back5(i32* %p) {
202 ; CHECK-LABEL: write_back5
203 ; CHECK-NEXT: load
204 ; CHECK-NEXT: store
205 ; CHECK-NEXT: ret
206 %v = load atomic i32, i32* %p unordered, align 4
207 store atomic i32 %v, i32* %p seq_cst, align 4
208 ret void
209 }
210
211 define void @write_back6(i32* %p) {
212 ; CHECK-LABEL: write_back6
213 ; CHECK-NEXT: load
214 ; CHECK-NEXT: ret
215 %v = load atomic i32, i32* %p seq_cst, align 4
216 store atomic i32 %v, i32* %p unordered, align 4
217 ret void
218 }
219
220 define void @write_back7(i32* %p) {
221 ; CHECK-LABEL: write_back7
222 ; CHECK-NEXT: load
223 ; CHECK-NEXT: ret
224 %v = load atomic volatile i32, i32* %p seq_cst, align 4
225 store atomic i32 %v, i32* %p unordered, align 4
226 ret void
227 }
228
116 !0 = !{!4, !4, i64 0} 229 !0 = !{!4, !4, i64 0}
117 !1 = !{!"omnipotent char", !2} 230 !1 = !{!"omnipotent char", !2}
118 !2 = !{!"Simple C/C++ TBAA"} 231 !2 = !{!"Simple C/C++ TBAA"}
119 !3 = !{!"float", !1} 232 !3 = !{!"float", !1}
120 !4 = !{!"int", !1} 233 !4 = !{!"int", !1}