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comparison docs/WritingAnLLVMBackend.rst @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
parents 1172e4bd9c6f
children 3a76565eade5
comparison
equal deleted inserted replaced
120:1172e4bd9c6f 121:803732b1fca8
591 namespace SP { // Register class instances 591 namespace SP { // Register class instances
592 DFPRegsClass DFPRegsRegClass; 592 DFPRegsClass DFPRegsRegClass;
593 FPRegsClass FPRegsRegClass; 593 FPRegsClass FPRegsRegClass;
594 IntRegsClass IntRegsRegClass; 594 IntRegsClass IntRegsRegClass;
595 ... 595 ...
596 // IntRegs Sub-register Classess... 596 // IntRegs Sub-register Classes...
597 static const TargetRegisterClass* const IntRegsSubRegClasses [] = { 597 static const TargetRegisterClass* const IntRegsSubRegClasses [] = {
598 NULL 598 NULL
599 }; 599 };
600 ... 600 ...
601 // IntRegs Super-register Classess... 601 // IntRegs Super-register Classes..
602 static const TargetRegisterClass* const IntRegsSuperRegClasses [] = { 602 static const TargetRegisterClass* const IntRegsSuperRegClasses [] = {
603 NULL 603 NULL
604 }; 604 };
605 ... 605 ...
606 // IntRegs Register Class sub-classes... 606 // IntRegs Register Class sub-classes...
1009 1009
1010 Instruction itineraries can be queried using MCDesc::getSchedClass(). The 1010 Instruction itineraries can be queried using MCDesc::getSchedClass(). The
1011 value can be named by an enumemation in llvm::XXX::Sched namespace generated 1011 value can be named by an enumemation in llvm::XXX::Sched namespace generated
1012 by TableGen in XXXGenInstrInfo.inc. The name of the schedule classes are 1012 by TableGen in XXXGenInstrInfo.inc. The name of the schedule classes are
1013 the same as provided in XXXSchedule.td plus a default NoItinerary class. 1013 the same as provided in XXXSchedule.td plus a default NoItinerary class.
1014
1015 The schedule models are generated by TableGen by the SubtargetEmitter,
1016 using the ``CodeGenSchedModels`` class. This is distinct from the itinerary
1017 method of specifying machine resource use. The tool ``utils/schedcover.py``
1018 can be used to determine which instructions have been covered by the
1019 schedule model description and which haven't. The first step is to use the
1020 instructions below to create an output file. Then run ``schedcover.py`` on the
1021 output file:
1022
1023 .. code-block:: shell
1024
1025 $ <src>/utils/schedcover.py <build>/lib/Target/AArch64/tblGenSubtarget.with
1026 instruction, default, CortexA53Model, CortexA57Model, CycloneModel, ExynosM1Model, FalkorModel, KryoModel, ThunderX2T99Model, ThunderXT8XModel
1027 ABSv16i8, WriteV, , , CyWriteV3, M1WriteNMISC1, FalkorWr_2VXVY_2cyc, KryoWrite_2cyc_XY_XY_150ln, ,
1028 ABSv1i64, WriteV, , , CyWriteV3, M1WriteNMISC1, FalkorWr_1VXVY_2cyc, KryoWrite_2cyc_XY_noRSV_67ln, ,
1029 ...
1030
1031 To capture the debug output from generating a schedule model, change to the
1032 appropriate target directory and use the following command:
1033 command with the ``subtarget-emitter`` debug option:
1034
1035 .. code-block:: shell
1036
1037 $ <build>/bin/llvm-tblgen -debug-only=subtarget-emitter -gen-subtarget \
1038 -I <src>/lib/Target/<target> -I <src>/include \
1039 -I <src>/lib/Target <src>/lib/Target/<target>/<target>.td \
1040 -o <build>/lib/Target/<target>/<target>GenSubtargetInfo.inc.tmp \
1041 > tblGenSubtarget.dbg 2>&1
1042
1043 Where ``<build>`` is the build directory, ``src`` is the source directory,
1044 and ``<target>`` is the name of the target.
1045 To double check that the above command is what is needed, one can capture the
1046 exact TableGen command from a build by using:
1047
1048 .. code-block:: shell
1049
1050 $ VERBOSE=1 make ...
1051
1052 and search for ``llvm-tblgen`` commands in the output.
1053
1014 1054
1015 Instruction Relation Mapping 1055 Instruction Relation Mapping
1016 ---------------------------- 1056 ----------------------------
1017 1057
1018 This TableGen feature is used to relate instructions with each other. It is 1058 This TableGen feature is used to relate instructions with each other. It is