CbC/CbC_llvm: lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp comparison

comparison lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @ 121:803732b1fca8

LLVM 5.0

author	kono
date	Fri, 27 Oct 2017 17:07:41 +0900
parents	1172e4bd9c6f
children	3a76565eade5

comparison

equal deleted inserted replaced

-:1172e4bd9c6f
+:803732b1fca8
-//===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===//
+//===- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ----===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 // with illegal types, so it's okay to put off legalizing them until
 // SelectionDAG::Legalize runs.
 //
 //===----------------------------------------------------------------------===//
+#include "llvm/ADT/APInt.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/CodeGen/ISDOpcodes.h"
+#include "llvm/CodeGen/MachineMemOperand.h"
+#include "llvm/CodeGen/MachineValueType.h"
 #include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/ValueTypes.h"
+#include "llvm/IR/DataLayout.h"
+#include "llvm/Support/Casting.h"
+#include "llvm/Support/Compiler.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/MathExtras.h"
 #include "llvm/Target/TargetLowering.h"
+#include <cassert>
+#include <cstdint>
+#include <iterator>
+#include <utility>
 using namespace llvm;
 namespace {
 class VectorLegalizer {
 SelectionDAG& DAG;
 const TargetLowering &TLI;
-bool Changed; // Keep track of whether anything changed
+bool Changed = false; // Keep track of whether anything changed
 /// For nodes that are of legal width, and that have more than one use, this
 /// map indicates what regularized operand to use.  This allows us to avoid
 /// legalizing the same thing more than once.
 SmallDenseMap<SDValue, SDValue, 64> LegalizedNodes;
 SDValue ExpandVSELECT(SDValue Op);
 SDValue ExpandSELECT(SDValue Op);
 SDValue ExpandLoad(SDValue Op);
 SDValue ExpandStore(SDValue Op);
 SDValue ExpandFNEG(SDValue Op);
+SDValue ExpandFSUB(SDValue Op);
 SDValue ExpandBITREVERSE(SDValue Op);
 SDValue ExpandCTLZ(SDValue Op);
 SDValue ExpandCTTZ_ZERO_UNDEF(SDValue Op);
 /// \brief Implements vector promotion.
 /// It is promoted to the next size up integer type.  The result is then
 /// truncated back to the original type.
 SDValue PromoteFP_TO_INT(SDValue Op, bool isSigned);
 public:
+VectorLegalizer(SelectionDAG& dag) :
+DAG(dag), TLI(dag.getTargetLoweringInfo()) {}
 /// \brief Begin legalizer the vector operations in the DAG.
 bool Run();
-VectorLegalizer(SelectionDAG& dag) :
-DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
 };
+} // end anonymous namespace
 bool VectorLegalizer::Run() {
 // Before we start legalizing vector nodes, check if there are any vectors.
 bool HasVectors = false;
 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
 "There are still live users of the old chain!");
 return LegalizeOp(Lowered);
 }
 return TranslateLegalizeResults(Op, Lowered);
 }
+LLVM_FALLTHROUGH;
 case TargetLowering::Expand:
 Changed = true;
 return LegalizeOp(ExpandLoad(Op));
 }
 } else if (Op.getOpcode() == ISD::STORE) {
 case ISD::ZERO_EXTEND_VECTOR_INREG:
 case ISD::SMIN:
 case ISD::SMAX:
 case ISD::UMIN:
 case ISD::UMAX:
+case ISD::SMUL_LOHI:
+case ISD::UMUL_LOHI:
 QueryType = Node->getValueType(0);
 break;
 case ISD::FP_ROUND_INREG:
 QueryType = cast<VTSDNode>(Node->getOperand(1))->getVT();
 break;
 "Can't promote a vector with multiple results!");
 EVT VT = Op.getValueType();
 EVT NewVT;
 unsigned NewOpc;
-while (1) {
+while (true) {
 NewVT = VT.widenIntegerVectorElementType(*DAG.getContext());
 assert(NewVT.isSimple() && "Promoting to a non-simple vector type!");
 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) {
 NewOpc = ISD::FP_TO_SINT;
 break;
 SDLoc loc(Op);
 SDValue promoted  = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0));
 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT, promoted);
 }
 SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
 EVT SrcVT = LD->getMemoryVT();
 EVT SrcEltVT = SrcVT.getScalarType();
 unsigned NumElem = SrcVT.getVectorNumElements();
 SDValue NewChain;
 SDValue Value;
 if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
 SDLoc dl(Op);
 }
 Vals.push_back(Lo);
 }
 NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
-Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
+Value = DAG.getBuildVector(Op.getNode()->getValueType(0), dl, Vals);
-Op.getNode()->getValueType(0), Vals);
 } else {
 SDValue Scalarized = TLI.scalarizeVectorLoad(LD, DAG);
 NewChain = Scalarized.getValue(1);
 Value = Scalarized.getValue(0);
 return ExpandSELECT(Op);
 case ISD::UINT_TO_FP:
 return ExpandUINT_TO_FLOAT(Op);
 case ISD::FNEG:
 return ExpandFNEG(Op);
+case ISD::FSUB:
+return ExpandFSUB(Op);
 case ISD::SETCC:
 return UnrollVSETCC(Op);
 case ISD::BITREVERSE:
 return ExpandBITREVERSE(Op);
 case ISD::CTLZ:
 SDValue Op2 = Op.getOperand(2);
 assert(VT.isVector() && !Mask.getValueType().isVector()
 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
-unsigned NumElem = VT.getVectorNumElements();
 // If we can't even use the basic vector operations of
 // AND,OR,XOR, we will have to scalarize the op.
 // Notice that the operation may be 'promoted' which means that it is
 // 'bitcasted' to another type which is handled.
 // Also, we need to be able to construct a splat vector using BUILD_VECTOR.
 DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), DL,
 BitTy),
 DAG.getConstant(0, DL, BitTy));
 // Broadcast the mask so that the entire vector is all-one or all zero.
-SmallVector<SDValue, 8> Ops(NumElem, Mask);
+Mask = DAG.getSplatBuildVector(MaskTy, DL, Mask);
-Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, Ops);
 // Bitcast the operands to be the same type as the mask.
 // This is needed when we select between FP types because
 // the mask is a vector of integers.
 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
 SDValue Zero = DAG.getConstantFP(-0.0, DL, Op.getValueType());
 // TODO: If FNEG had fast-math-flags, they'd get propagated to this FSUB.
 return DAG.getNode(ISD::FSUB, DL, Op.getValueType(),
 Zero, Op.getOperand(0));
 }
+return DAG.UnrollVectorOp(Op.getNode());
+}
+SDValue VectorLegalizer::ExpandFSUB(SDValue Op) {
+// For floating-point values, (a-b) is the same as a+(-b). If FNEG is legal,
+// we can defer this to operation legalization where it will be lowered as
+// a+(-b).
+EVT VT = Op.getValueType();
+if (TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
+TLI.isOperationLegalOrCustom(ISD::FADD, VT))
+return Op; // Defer to LegalizeDAG
 return DAG.UnrollVectorOp(Op.getNode());
 }
 SDValue VectorLegalizer::ExpandCTLZ(SDValue Op) {
 EVT VT = Op.getValueType();
 Ops[i] = DAG.getSelect(dl, EltVT, Ops[i],
 DAG.getConstant(APInt::getAllOnesValue
 (EltVT.getSizeInBits()), dl, EltVT),
 DAG.getConstant(0, dl, EltVT));
 }
-return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
+return DAG.getBuildVector(VT, dl, Ops);
-}
 }
 bool SelectionDAG::LegalizeVectors() {
 return VectorLegalizer(*this).Run();
 }

Mercurial > hg > CbC > CbC_llvm

comparison lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @ 121:803732b1fca8