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comparison lib/Target/Hexagon/HexagonBlockRanges.h @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
parents 1172e4bd9c6f
children c2174574ed3a
comparison
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120:1172e4bd9c6f 121:803732b1fca8
1 //===--- HexagonBlockRanges.h ---------------------------------------------===// 1 //===- HexagonBlockRanges.h -------------------------------------*- C++ -*-===//
2 // 2 //
3 // The LLVM Compiler Infrastructure 3 // The LLVM Compiler Infrastructure
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 #ifndef HEXAGON_BLOCK_RANGES_H 9
10 #define HEXAGON_BLOCK_RANGES_H 10 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONBLOCKRANGES_H
11 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONBLOCKRANGES_H
11 12
12 #include "llvm/ADT/BitVector.h" 13 #include "llvm/ADT/BitVector.h"
13 #include "llvm/CodeGen/MachineBasicBlock.h" 14 #include <cassert>
14 #include "llvm/MC/MCRegisterInfo.h" // For MCPhysReg.
15 #include <map> 15 #include <map>
16 #include <set> 16 #include <set>
17 #include <utility>
17 #include <vector> 18 #include <vector>
18 19
19 namespace llvm { 20 namespace llvm {
20 class Function; 21
21 class HexagonSubtarget; 22 class HexagonSubtarget;
22 class MachineBasicBlock; 23 class MachineBasicBlock;
23 class MachineFunction; 24 class MachineFunction;
24 class MachineInstr; 25 class MachineInstr;
25 class MCInstrDesc; 26 class MachineRegisterInfo;
26 class raw_ostream; 27 class raw_ostream;
27 class TargetInstrInfo; 28 class TargetInstrInfo;
28 class TargetRegisterClass; 29 class TargetRegisterInfo;
29 class TargetRegisterInfo;
30 class Type;
31 30
32 struct HexagonBlockRanges { 31 struct HexagonBlockRanges {
33 HexagonBlockRanges(MachineFunction &MF); 32 HexagonBlockRanges(MachineFunction &MF);
34 33
35 struct RegisterRef { 34 struct RegisterRef {
36 unsigned Reg, Sub; 35 unsigned Reg, Sub;
36
37 bool operator<(RegisterRef R) const { 37 bool operator<(RegisterRef R) const {
38 return Reg < R.Reg || (Reg == R.Reg && Sub < R.Sub); 38 return Reg < R.Reg || (Reg == R.Reg && Sub < R.Sub);
39 } 39 }
40 }; 40 };
41 typedef std::set<RegisterRef> RegisterSet; 41 using RegisterSet = std::set<RegisterRef>;
42 42
43 // This is to represent an "index", which is an abstraction of a position 43 // This is to represent an "index", which is an abstraction of a position
44 // of an instruction within a basic block. 44 // of an instruction within a basic block.
45 class IndexType { 45 class IndexType {
46 public: 46 public:
48 None = 0, 48 None = 0,
49 Entry = 1, 49 Entry = 1,
50 Exit = 2, 50 Exit = 2,
51 First = 11 // 10th + 1st 51 First = 11 // 10th + 1st
52 }; 52 };
53
54 IndexType() {}
55 IndexType(unsigned Idx) : Index(Idx) {}
56
53 static bool isInstr(IndexType X) { return X.Index >= First; } 57 static bool isInstr(IndexType X) { return X.Index >= First; }
54 58
55 IndexType() : Index(None) {}
56 IndexType(unsigned Idx) : Index(Idx) {}
57 operator unsigned() const; 59 operator unsigned() const;
58 bool operator== (unsigned x) const; 60 bool operator== (unsigned x) const;
59 bool operator== (IndexType Idx) const; 61 bool operator== (IndexType Idx) const;
60 bool operator!= (unsigned x) const; 62 bool operator!= (unsigned x) const;
61 bool operator!= (IndexType Idx) const; 63 bool operator!= (IndexType Idx) const;
66 68
67 private: 69 private:
68 bool operator> (IndexType Idx) const; 70 bool operator> (IndexType Idx) const;
69 bool operator>= (IndexType Idx) const; 71 bool operator>= (IndexType Idx) const;
70 72
71 unsigned Index; 73 unsigned Index = None;
72 }; 74 };
73 75
74 // A range of indices, essentially a representation of a live range. 76 // A range of indices, essentially a representation of a live range.
75 // This is also used to represent "dead ranges", i.e. ranges where a 77 // This is also used to represent "dead ranges", i.e. ranges where a
76 // register is dead. 78 // register is dead.
77 class IndexRange : public std::pair<IndexType,IndexType> { 79 class IndexRange : public std::pair<IndexType,IndexType> {
78 public: 80 public:
79 IndexRange() : Fixed(false), TiedEnd(false) {} 81 IndexRange() = default;
80 IndexRange(IndexType Start, IndexType End, bool F = false, bool T = false) 82 IndexRange(IndexType Start, IndexType End, bool F = false, bool T = false)
81 : std::pair<IndexType,IndexType>(Start, End), Fixed(F), TiedEnd(T) {} 83 : std::pair<IndexType,IndexType>(Start, End), Fixed(F), TiedEnd(T) {}
84
82 IndexType start() const { return first; } 85 IndexType start() const { return first; }
83 IndexType end() const { return second; } 86 IndexType end() const { return second; }
84 87
85 bool operator< (const IndexRange &A) const { 88 bool operator< (const IndexRange &A) const {
86 return start() < A.start(); 89 return start() < A.start();
87 } 90 }
91
88 bool overlaps(const IndexRange &A) const; 92 bool overlaps(const IndexRange &A) const;
89 bool contains(const IndexRange &A) const; 93 bool contains(const IndexRange &A) const;
90 void merge(const IndexRange &A); 94 void merge(const IndexRange &A);
91 95
92 bool Fixed; // Can be renamed? "Fixed" means "no". 96 bool Fixed = false; // Can be renamed? "Fixed" means "no".
93 bool TiedEnd; // The end is not a use, but a dead def tied to a use. 97 bool TiedEnd = false; // The end is not a use, but a dead def tied to a use.
94 98
95 private: 99 private:
96 void setStart(const IndexType &S) { first = S; } 100 void setStart(const IndexType &S) { first = S; }
97 void setEnd(const IndexType &E) { second = E; } 101 void setEnd(const IndexType &E) { second = E; }
98 }; 102 };
105 push_back(IndexRange(Start, End, Fixed, TiedEnd)); 109 push_back(IndexRange(Start, End, Fixed, TiedEnd));
106 } 110 }
107 void add(const IndexRange &Range) { 111 void add(const IndexRange &Range) {
108 push_back(Range); 112 push_back(Range);
109 } 113 }
114
110 void include(const RangeList &RL); 115 void include(const RangeList &RL);
111 void unionize(bool MergeAdjacent = false); 116 void unionize(bool MergeAdjacent = false);
112 void subtract(const IndexRange &Range); 117 void subtract(const IndexRange &Range);
113 118
114 private: 119 private:
116 }; 121 };
117 122
118 class InstrIndexMap { 123 class InstrIndexMap {
119 public: 124 public:
120 InstrIndexMap(MachineBasicBlock &B); 125 InstrIndexMap(MachineBasicBlock &B);
126
121 MachineInstr *getInstr(IndexType Idx) const; 127 MachineInstr *getInstr(IndexType Idx) const;
122 IndexType getIndex(MachineInstr *MI) const; 128 IndexType getIndex(MachineInstr *MI) const;
123 MachineBasicBlock &getBlock() const { return Block; } 129 MachineBasicBlock &getBlock() const { return Block; }
124 IndexType getPrevIndex(IndexType Idx) const; 130 IndexType getPrevIndex(IndexType Idx) const;
125 IndexType getNextIndex(IndexType Idx) const; 131 IndexType getNextIndex(IndexType Idx) const;
126 void replaceInstr(MachineInstr *OldMI, MachineInstr *NewMI); 132 void replaceInstr(MachineInstr *OldMI, MachineInstr *NewMI);
127 133
128 friend raw_ostream &operator<< (raw_ostream &OS, const InstrIndexMap &Map); 134 friend raw_ostream &operator<< (raw_ostream &OS, const InstrIndexMap &Map);
135
129 IndexType First, Last; 136 IndexType First, Last;
130 137
131 private: 138 private:
132 MachineBasicBlock &Block; 139 MachineBasicBlock &Block;
133 std::map<IndexType,MachineInstr*> Map; 140 std::map<IndexType,MachineInstr*> Map;
134 }; 141 };
135 142
136 typedef std::map<RegisterRef,RangeList> RegToRangeMap; 143 using RegToRangeMap = std::map<RegisterRef, RangeList>;
144
137 RegToRangeMap computeLiveMap(InstrIndexMap &IndexMap); 145 RegToRangeMap computeLiveMap(InstrIndexMap &IndexMap);
138 RegToRangeMap computeDeadMap(InstrIndexMap &IndexMap, RegToRangeMap &LiveMap); 146 RegToRangeMap computeDeadMap(InstrIndexMap &IndexMap, RegToRangeMap &LiveMap);
139 static RegisterSet expandToSubRegs(RegisterRef R, 147 static RegisterSet expandToSubRegs(RegisterRef R,
140 const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI); 148 const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI);
141 149
142 struct PrintRangeMap { 150 struct PrintRangeMap {
143 PrintRangeMap(const RegToRangeMap &M, const TargetRegisterInfo &I) 151 PrintRangeMap(const RegToRangeMap &M, const TargetRegisterInfo &I)
144 : Map(M), TRI(I) {} 152 : Map(M), TRI(I) {}
145 153
146 friend raw_ostream &operator<< (raw_ostream &OS, const PrintRangeMap &P); 154 friend raw_ostream &operator<< (raw_ostream &OS, const PrintRangeMap &P);
155
147 private: 156 private:
148 const RegToRangeMap &Map; 157 const RegToRangeMap &Map;
149 const TargetRegisterInfo &TRI; 158 const TargetRegisterInfo &TRI;
150 }; 159 };
151 160
160 const HexagonSubtarget &HST; 169 const HexagonSubtarget &HST;
161 const TargetInstrInfo &TII; 170 const TargetInstrInfo &TII;
162 const TargetRegisterInfo &TRI; 171 const TargetRegisterInfo &TRI;
163 BitVector Reserved; 172 BitVector Reserved;
164 }; 173 };
165
166 174
167 inline HexagonBlockRanges::IndexType::operator unsigned() const { 175 inline HexagonBlockRanges::IndexType::operator unsigned() const {
168 assert(Index >= First); 176 assert(Index >= First);
169 return Index; 177 return Index;
170 } 178 }
222 230
223 inline bool HexagonBlockRanges::IndexType::operator<= (IndexType Idx) const { 231 inline bool HexagonBlockRanges::IndexType::operator<= (IndexType Idx) const {
224 return operator==(Idx) || operator<(Idx); 232 return operator==(Idx) || operator<(Idx);
225 } 233 }
226 234
227
228 raw_ostream &operator<< (raw_ostream &OS, HexagonBlockRanges::IndexType Idx); 235 raw_ostream &operator<< (raw_ostream &OS, HexagonBlockRanges::IndexType Idx);
229 raw_ostream &operator<< (raw_ostream &OS, 236 raw_ostream &operator<< (raw_ostream &OS,
230 const HexagonBlockRanges::IndexRange &IR); 237 const HexagonBlockRanges::IndexRange &IR);
231 raw_ostream &operator<< (raw_ostream &OS, 238 raw_ostream &operator<< (raw_ostream &OS,
232 const HexagonBlockRanges::RangeList &RL); 239 const HexagonBlockRanges::RangeList &RL);
233 raw_ostream &operator<< (raw_ostream &OS, 240 raw_ostream &operator<< (raw_ostream &OS,
234 const HexagonBlockRanges::InstrIndexMap &M); 241 const HexagonBlockRanges::InstrIndexMap &M);
235 raw_ostream &operator<< (raw_ostream &OS, 242 raw_ostream &operator<< (raw_ostream &OS,
236 const HexagonBlockRanges::PrintRangeMap &P); 243 const HexagonBlockRanges::PrintRangeMap &P);
237 244
238 } // namespace llvm 245 } // end namespace llvm
239 246
240 #endif 247 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONBLOCKRANGES_H