CbC/CbC_llvm: lib/Target/Hexagon/HexagonExpandCondsets.cpp comparison

comparison lib/Target/Hexagon/HexagonExpandCondsets.cpp @ 121:803732b1fca8

LLVM 5.0

author	kono
date	Fri, 27 Oct 2017 17:07:41 +0900
parents	1172e4bd9c6f
children	3a76565eade5

comparison

equal deleted inserted replaced

-:1172e4bd9c6f
+:803732b1fca8
-//===--- HexagonExpandCondsets.cpp ----------------------------------------===//
+//===- HexagonExpandCondsets.cpp ------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 // that, the initial splitting will not add any implicit uses. These
 // implicit uses will be added later, after predication. The extra price,
 // however, is that finding the locations where the implicit uses need
 // to be added, and updating the live ranges will be more involved.
-#define DEBUG_TYPE "expand-condsets"
+#include "HexagonInstrInfo.h"
+#include "HexagonRegisterInfo.h"
-#include "HexagonTargetMachine.h"
+#include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/SetVector.h"
-#include "llvm/CodeGen/Passes.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringRef.h"
 #include "llvm/CodeGen/LiveInterval.h"
 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineDominators.h"
 #include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/SlotIndexes.h"
-#include "llvm/Target/TargetMachine.h"
+#include "llvm/IR/DebugLoc.h"
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/IR/Function.h"
+#include "llvm/MC/LaneBitmask.h"
+#include "llvm/Pass.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetRegisterInfo.h"
-#include <algorithm>
+#include "llvm/Target/TargetSubtargetInfo.h"
+#include <cassert>
 #include <iterator>
 #include <set>
 #include <utility>
+#define DEBUG_TYPE "expand-condsets"
 using namespace llvm;
 static cl::opt<unsigned> OptTfrLimit("expand-condsets-tfr-limit",
 cl::init(~0U), cl::Hidden, cl::desc("Max number of mux expansions"));
 static cl::opt<unsigned> OptCoaLimit("expand-condsets-coa-limit",
 cl::init(~0U), cl::Hidden, cl::desc("Max number of segment coalescings"));
 namespace llvm {
 void initializeHexagonExpandCondsetsPass(PassRegistry&);
 FunctionPass *createHexagonExpandCondsets();
-}
+} // end namespace llvm
 namespace {
 class HexagonExpandCondsets : public MachineFunctionPass {
 public:
 static char ID;
-HexagonExpandCondsets() :
-MachineFunctionPass(ID), HII(0), TRI(0), MRI(0),
+HexagonExpandCondsets() : MachineFunctionPass(ID) {
-LIS(0), CoaLimitActive(false),
-TfrLimitActive(false), CoaCounter(0), TfrCounter(0) {
 if (OptCoaLimit.getPosition())
 CoaLimitActive = true, CoaLimit = OptCoaLimit;
 if (OptTfrLimit.getPosition())
 TfrLimitActive = true, TfrLimit = OptTfrLimit;
 initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
 }
 StringRef getPassName() const override { return "Hexagon Expand Condsets"; }
 void getAnalysisUsage(AnalysisUsage &AU) const override {
 AU.addRequired<LiveIntervals>();
 AU.addPreserved<LiveIntervals>();
 AU.addPreserved<SlotIndexes>();
 AU.addRequired<MachineDominatorTree>();
 AU.addPreserved<MachineDominatorTree>();
 MachineFunctionPass::getAnalysisUsage(AU);
 }
 bool runOnMachineFunction(MachineFunction &MF) override;
 private:
-const HexagonInstrInfo *HII;
+const HexagonInstrInfo *HII = nullptr;
-const TargetRegisterInfo *TRI;
+const TargetRegisterInfo *TRI = nullptr;
 MachineDominatorTree *MDT;
-MachineRegisterInfo *MRI;
+MachineRegisterInfo *MRI = nullptr;
-LiveIntervals *LIS;
+LiveIntervals *LIS = nullptr;
+bool CoaLimitActive = false;
-bool CoaLimitActive, TfrLimitActive;
+bool TfrLimitActive = false;
-unsigned CoaLimit, TfrLimit, CoaCounter, TfrCounter;
+unsigned CoaLimit;
+unsigned TfrLimit;
+unsigned CoaCounter = 0;
+unsigned TfrCounter = 0;
 struct RegisterRef {
 RegisterRef(const MachineOperand &Op) : Reg(Op.getReg()),
 Sub(Op.getSubReg()) {}
 RegisterRef(unsigned R = 0, unsigned S = 0) : Reg(R), Sub(S) {}
 bool operator== (RegisterRef RR) const {
 return Reg == RR.Reg && Sub == RR.Sub;
 }
 bool operator!= (RegisterRef RR) const { return !operator==(RR); }
 bool operator< (RegisterRef RR) const {
 return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub);
 }
 unsigned Reg, Sub;
 };
-typedef DenseMap<unsigned,unsigned> ReferenceMap;
+using ReferenceMap = DenseMap<unsigned, unsigned>;
 enum { Sub_Low = 0x1, Sub_High = 0x2, Sub_None = (Sub_Low | Sub_High) };
 enum { Exec_Then = 0x10, Exec_Else = 0x20 };
 unsigned getMaskForSub(unsigned Sub);
 bool isCondset(const MachineInstr &MI);
 LaneBitmask getLaneMask(unsigned Reg, unsigned Sub);
 void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec);
 bool isIntraBlocks(LiveInterval &LI);
 bool coalesceRegisters(RegisterRef R1, RegisterRef R2);
 bool coalesceSegments(const SmallVectorImpl<MachineInstr*> &Condsets,
 std::set<unsigned> &UpdRegs);
 };
-}
+} // end anonymous namespace
 char HexagonExpandCondsets::ID = 0;
 namespace llvm {
 char &HexagonExpandCondsetsID = HexagonExpandCondsets::ID;
-}
+} // end namespace llvm
 INITIALIZE_PASS_BEGIN(HexagonExpandCondsets, "expand-condsets",
 "Hexagon Expand Condsets", false, false)
 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
 break;
 }
 return false;
 }
 LaneBitmask HexagonExpandCondsets::getLaneMask(unsigned Reg, unsigned Sub) {
 assert(TargetRegisterInfo::isVirtualRegister(Reg));
 return Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)
 : MRI->getMaxLaneMaskForVReg(Reg);
 }
 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map,
 unsigned Exec) {
 unsigned Mask = getMaskForSub(RR.Sub) | Exec;
 ReferenceMap::iterator F = Map.find(RR.Reg);
 Map.insert(std::make_pair(RR.Reg, Mask));
 else
 F->second |= Mask;
 }
 bool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map,
 unsigned Exec) {
 ReferenceMap::iterator F = Map.find(RR.Reg);
 if (F == Map.end())
 return false;
 unsigned Mask = getMaskForSub(RR.Sub) | Exec;
 if (Mask & F->second)
 return true;
 return false;
 }
 void HexagonExpandCondsets::updateKillFlags(unsigned Reg) {
 auto KillAt = [this,Reg] (SlotIndex K, LaneBitmask LM) -> void {
 // Set the <kill> flag on a use of Reg whose lane mask is contained in LM.
 MachineInstr *MI = LIS->getInstructionFromIndex(K);
 if (WholeReg)
 KillAt(I->end, MRI->getMaxLaneMaskForVReg(Reg));
 }
 }
 void HexagonExpandCondsets::updateDeadsInRange(unsigned Reg, LaneBitmask LM,
 LiveRange &Range) {
 assert(TargetRegisterInfo::isVirtualRegister(Reg));
 if (Range.empty())
 return;
-auto IsRegDef = [this,Reg,LM] (MachineOperand &Op) -> bool {
+// Return two booleans: { def-modifes-reg, def-covers-reg }.
+auto IsRegDef = [this,Reg,LM] (MachineOperand &Op) -> std::pair<bool,bool> {
 if (!Op.isReg() || !Op.isDef())
-return false;
+return { false, false };
 unsigned DR = Op.getReg(), DSR = Op.getSubReg();
 if (!TargetRegisterInfo::isVirtualRegister(DR) || DR != Reg)
-return false;
+return { false, false };
 LaneBitmask SLM = getLaneMask(DR, DSR);
-return (SLM & LM) != 0;
+LaneBitmask A = SLM & LM;
+return { A.any(), A == SLM };
 };
 // The splitting step will create pairs of predicated definitions without
 // any implicit uses (since implicit uses would interfere with predication).
 // This can cause the reaching defs to become dead after live range
 LIS->extendToIndices(Range, ExtTo, Undefs);
 // Remove <dead> flags from all defs that are not dead after live range
 // extension, and collect all def operands. They will be used to generate
 // the necessary implicit uses.
+// At the same time, add <dead> flag to all defs that are actually dead.
+// This can happen, for example, when a mux with identical inputs is
+// replaced with a COPY: the use of the predicate register disappears and
+// the dead can become dead.
 std::set<RegisterRef> DefRegs;
 for (auto &Seg : Range) {
 if (!Seg.start.isRegister())
 continue;
 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
 for (auto &Op : DefI->operands()) {
-if (Seg.start.isDead() || !IsRegDef(Op))
+auto P = IsRegDef(Op);
-continue;
+if (P.second && Seg.end.isDead()) {
-DefRegs.insert(Op);
+Op.setIsDead(true);
-Op.setIsDead(false);
+} else if (P.first) {
-}
+DefRegs.insert(Op);
-}
+Op.setIsDead(false);
+}
-// Finally, add implicit uses to each predicated def that is reached
+}
+}
+// Now, add implicit uses to each predicated def that is reached
 // by other defs.
 for (auto &Seg : Range) {
 if (!Seg.start.isRegister() || !Range.liveAt(Seg.start.getPrevSlot()))
 continue;
 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
 if (!HII->isPredicated(*DefI))
 continue;
 // Construct the set of all necessary implicit uses, based on the def
-// operands in the instruction.
+// operands in the instruction. We need to tie the implicit uses to
-std::set<RegisterRef> ImpUses;
+// the corresponding defs.
-for (auto &Op : DefI->operands())
+std::map<RegisterRef,unsigned> ImpUses;
-if (Op.isReg() && Op.isDef() && DefRegs.count(Op))
+for (unsigned i = 0, e = DefI->getNumOperands(); i != e; ++i) {
-ImpUses.insert(Op);
+MachineOperand &Op = DefI->getOperand(i);
+if (!Op.isReg() || !DefRegs.count(Op))
+continue;
+if (Op.isDef()) {
+ImpUses.insert({Op, i});
+} else {
+// This function can be called for the same register with different
+// lane masks. If the def in this instruction was for the whole
+// register, we can get here more than once. Avoid adding multiple
+// implicit uses (or adding an implicit use when an explicit one is
+// present).
+ImpUses.erase(Op);
+}
+}
 if (ImpUses.empty())
 continue;
 MachineFunction &MF = *DefI->getParent()->getParent();
-for (RegisterRef R : ImpUses)
+for (std::pair<RegisterRef, unsigned> P : ImpUses) {
+RegisterRef R = P.first;
 MachineInstrBuilder(MF, DefI).addReg(R.Reg, RegState::Implicit, R.Sub);
-}
+DefI->tieOperands(P.second, DefI->getNumOperands()-1);
 }
+}
+}
 void HexagonExpandCondsets::updateDeadFlags(unsigned Reg) {
 LiveInterval &LI = LIS->getInterval(Reg);
 if (LI.hasSubRanges()) {
 for (LiveInterval::SubRange &S : LI.subranges()) {
 } else {
 updateDeadsInRange(Reg, MRI->getMaxLaneMaskForVReg(Reg), LI);
 }
 }
 void HexagonExpandCondsets::recalculateLiveInterval(unsigned Reg) {
 LIS->removeInterval(Reg);
 LIS->createAndComputeVirtRegInterval(Reg);
 }
 void HexagonExpandCondsets::removeInstr(MachineInstr &MI) {
 LIS->RemoveMachineInstrFromMaps(MI);
 MI.eraseFromParent();
 }
 void HexagonExpandCondsets::updateLiveness(std::set<unsigned> &RegSet,
 bool Recalc, bool UpdateKills, bool UpdateDeads) {
 UpdateKills |= UpdateDeads;
 for (auto R : RegSet) {
 updateKillFlags(R);
 LIS->getInterval(R).verify();
 }
 }
 /// Get the opcode for a conditional transfer of the value in SO (source
 /// operand). The condition (true/false) is given in Cond.
 unsigned HexagonExpandCondsets::getCondTfrOpcode(const MachineOperand &SO,
 bool IfTrue) {
 using namespace Hexagon;
 if (SO.isReg()) {
 unsigned PhysR;
 RegisterRef RS = SO;
 if (TargetRegisterInfo::isVirtualRegister(RS.Reg)) {
 const TargetRegisterClass *VC = MRI->getRegClass(RS.Reg);
 assert(TargetRegisterInfo::isPhysicalRegister(RS.Reg));
 PhysR = RS.Reg;
 }
 unsigned PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub);
 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS);
-switch (RC->getSize()) {
+switch (TRI->getRegSizeInBits(*RC)) {
-case 4:
+case 32:
 return IfTrue ? A2_tfrt : A2_tfrf;
-case 8:
+case 64:
 return IfTrue ? A2_tfrpt : A2_tfrpf;
 }
 llvm_unreachable("Invalid register operand");
 }
-if (SO.isImm() || SO.isFPImm())
+switch (SO.getType()) {
-return IfTrue ? C2_cmoveit : C2_cmoveif;
+case MachineOperand::MO_Immediate:
+case MachineOperand::MO_FPImmediate:
+case MachineOperand::MO_ConstantPoolIndex:
+case MachineOperand::MO_TargetIndex:
+case MachineOperand::MO_JumpTableIndex:
+case MachineOperand::MO_ExternalSymbol:
+case MachineOperand::MO_GlobalAddress:
+case MachineOperand::MO_BlockAddress:
+return IfTrue ? C2_cmoveit : C2_cmoveif;
+default:
+break;
+}
 llvm_unreachable("Unexpected source operand");
 }
 /// Generate a conditional transfer, copying the value SrcOp to the
 /// destination register DstR:DstSR, and using the predicate register from
 /// PredOp. The Cond argument specifies whether the predicate is to be
 /// if(PredOp), or if(!PredOp).
 .addReg(DstR, DstState, DstSR)
 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
 .addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg());
 } else {
 MIB = BuildMI(B, At, DL, HII->get(Opc))
 .addReg(DstR, DstState, DstSR)
 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
-.addOperand(SrcOp);
+.add(SrcOp);
 }
 DEBUG(dbgs() << "created an initial copy: " << *MIB);
 return &*MIB;
 }
 /// Replace a MUX instruction MI with a pair A2_tfrt/A2_tfrf. This function
 /// performs all necessary changes to complete the replacement.
 bool HexagonExpandCondsets::split(MachineInstr &MI,
 std::set<unsigned> &UpdRegs) {
 assert(MD.isDef());
 unsigned DR = MD.getReg(), DSR = MD.getSubReg();
 bool ReadUndef = MD.isUndef();
 MachineBasicBlock::iterator At = MI;
+auto updateRegs = [&UpdRegs] (const MachineInstr &MI) -> void {
+for (auto &Op : MI.operands())
+if (Op.isReg())
+UpdRegs.insert(Op.getReg());
+};
 // If this is a mux of the same register, just replace it with COPY.
 // Ideally, this would happen earlier, so that register coalescing would
 // see it.
 MachineOperand &ST = MI.getOperand(2);
 MachineOperand &SF = MI.getOperand(3);
 if (ST.isReg() && SF.isReg()) {
 RegisterRef RT(ST);
 if (RT == RegisterRef(SF)) {
+// Copy regs to update first.
+updateRegs(MI);
 MI.setDesc(HII->get(TargetOpcode::COPY));
 unsigned S = getRegState(ST);
 while (MI.getNumOperands() > 1)
 MI.RemoveOperand(MI.getNumOperands()-1);
 MachineFunction &MF = *MI.getParent()->getParent();
 genCondTfrFor(SF, At, DR, DSR, MP, false, ReadUndef, true);
 LIS->InsertMachineInstrInMaps(*TfrT);
 LIS->InsertMachineInstrInMaps(*TfrF);
 // Will need to recalculate live intervals for all registers in MI.
-for (auto &Op : MI.operands())
+updateRegs(MI);
-if (Op.isReg())
-UpdRegs.insert(Op.getReg());
 removeInstr(MI);
 return true;
 }
 for (auto &Mo : MI->memoperands())
 if (Mo->isVolatile())
 return false;
 return true;
 }
 /// Find the reaching definition for a predicated use of RD. The RD is used
 /// under the conditions given by PredR and Cond, and this function will ignore
 /// definitions that set RD under the opposite conditions.
 MachineInstr *HexagonExpandCondsets::getReachingDefForPred(RegisterRef RD,
 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond) {
 MachineBasicBlock &B = *UseIt->getParent();
 MachineBasicBlock::iterator I = UseIt, S = B.begin();
 if (I == S)
-return 0;
+return nullptr;
 bool PredValid = true;
 do {
 --I;
 MachineInstr *MI = &*I;
 // If we are looking for vreg1:loreg, we can skip vreg1:hireg, but
 // not vreg1 (w/o subregisters).
 if (RR.Sub == RD.Sub)
 return MI;
 if (RR.Sub == 0 || RD.Sub == 0)
-return 0;
+return nullptr;
 // We have different subregisters, so we can continue looking.
 }
 } while (I != S);
-return 0;
+return nullptr;
 }
 /// Check if the instruction MI can be safely moved over a set of instructions
 /// whose side-effects (in terms of register defs and uses) are expressed in
 /// the maps Defs and Uses. These maps reflect the conditional defs and uses
 /// that depend on the same predicate register to allow moving instructions
 return false;
 }
 return true;
 }
 /// Check if the instruction accessing memory (TheI) can be moved to the
 /// location ToI.
 bool HexagonExpandCondsets::canMoveMemTo(MachineInstr &TheI, MachineInstr &ToI,
 bool IsDown) {
 bool IsLoad = TheI.mayLoad(), IsStore = TheI.mayStore();
 if (Conflict)
 return false;
 }
 return true;
 }
 /// Generate a predicated version of MI (where the condition is given via
 /// PredR and Cond) at the point indicated by Where.
 void HexagonExpandCondsets::predicateAt(const MachineOperand &DefOp,
 MachineInstr &MI,
 MB.addReg(PredOp.getReg(), PredOp.isUndef() ? RegState::Undef : 0,
 PredOp.getSubReg());
 while (Ox < NP) {
 MachineOperand &MO = MI.getOperand(Ox);
 if (!MO.isReg() || !MO.isImplicit())
-MB.addOperand(MO);
+MB.add(MO);
 Ox++;
 }
 MachineFunction &MF = *B.getParent();
 MachineInstr::mmo_iterator I = MI.memoperands_begin();
 for (auto &Op : NewI->operands())
 if (Op.isReg())
 UpdRegs.insert(Op.getReg());
 }
 /// In the range [First, Last], rename all references to the "old" register RO
 /// to the "new" register RN, but only in instructions predicated on the given
 /// condition.
 void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN,
 assert(!Op.isDef() && "Not expecting a def");
 }
 }
 }
 /// For a given conditional copy, predicate the definition of the source of
 /// the copy under the given condition (using the same predicate register as
 /// the copy).
 bool HexagonExpandCondsets::predicate(MachineInstr &TfrI, bool Cond,
 std::set<unsigned> &UpdRegs) {
 // Check if the predicate register is valid between DefI and TfrI.
 // If it is, we can then ignore instructions predicated on the negated
 // conditions when collecting def and use information.
 bool PredValid = true;
 for (MachineBasicBlock::iterator I = std::next(DefIt); I != TfrIt; ++I) {
-if (!I->modifiesRegister(PredR, 0))
+if (!I->modifiesRegister(PredR, nullptr))
 continue;
 PredValid = false;
 break;
 }
 removeInstr(TfrI);
 removeInstr(*DefI);
 return true;
 }
 /// Predicate all cases of conditional copies in the specified block.
 bool HexagonExpandCondsets::predicateInBlock(MachineBasicBlock &B,
 std::set<unsigned> &UpdRegs) {
 bool Changed = false;
 }
 }
 return Changed;
 }
 bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) {
 if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))
 return false;
 const TargetRegisterClass *RC = MRI->getRegClass(RR.Reg);
 if (RC == &Hexagon::IntRegsRegClass) {
 BW = (RR.Sub != 0) ? 32 : 64;
 return true;
 }
 return false;
 }
 bool HexagonExpandCondsets::isIntraBlocks(LiveInterval &LI) {
 for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) {
 LiveRange::Segment &LR = *I;
 // Range must start at a register...
 return false;
 }
 return true;
 }
 bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) {
 if (CoaLimitActive) {
 if (CoaCounter >= CoaLimit)
 return false;
 CoaCounter++;
 return false;
 MRI->replaceRegWith(R2.Reg, R1.Reg);
 // Move all live segments from L2 to L1.
-typedef DenseMap<VNInfo*,VNInfo*> ValueInfoMap;
+using ValueInfoMap = DenseMap<VNInfo *, VNInfo *>;
 ValueInfoMap VM;
 for (LiveInterval::iterator I = L2.begin(), E = L2.end(); I != E; ++I) {
 VNInfo *NewVN, *OldVN = I->valno;
 ValueInfoMap::iterator F = VM.find(OldVN);
 if (F == VM.end()) {
 DEBUG(dbgs() << "coalesced: " << L1 << "\n");
 L1.verify();
 return true;
 }
 /// Attempt to coalesce one of the source registers to a MUX instruction with
 /// the destination register. This could lead to having only one predicated
 /// instruction in the end instead of two.
 bool HexagonExpandCondsets::coalesceSegments(
 Changed |= Done;
 }
 return Changed;
 }
 bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) {
 if (skipFunction(*MF.getFunction()))
 return false;
 HII = static_cast<const HexagonInstrInfo*>(MF.getSubtarget().getInstrInfo());
 });
 return Changed;
 }
 //===----------------------------------------------------------------------===//
 //                         Public Constructor Functions
 //===----------------------------------------------------------------------===//
 FunctionPass *llvm::createHexagonExpandCondsets() {

Mercurial > hg > CbC > CbC_llvm

comparison lib/Target/Hexagon/HexagonExpandCondsets.cpp @ 121:803732b1fca8