CbC/CbC_llvm: lib/Target/SystemZ/SystemZInstrFormats.td comparison

comparison lib/Target/SystemZ/SystemZInstrFormats.td @ 121:803732b1fca8

LLVM 5.0

author	kono
date	Fri, 27 Oct 2017 17:07:41 +0900
parents	1172e4bd9c6f
children	3a76565eade5

comparison

equal deleted inserted replaced

-:1172e4bd9c6f
+:803732b1fca8
 let Inst{15-8} = op;
 let Inst{7-0}  = I1;
 }
+class InstIE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+: InstSystemZ<4, outs, ins, asmstr, pattern> {
+field bits<32> Inst;
+field bits<32> SoftFail = 0;
+bits<4> I1;
+bits<4> I2;
+let Inst{31-16} = op;
+let Inst{15-8}  = 0;
+let Inst{7-4}   = I1;
+let Inst{3-0}   = I2;
+}
+class InstMII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+: InstSystemZ<6, outs, ins, asmstr, pattern> {
+field bits<48> Inst;
+field bits<48> SoftFail = 0;
+bits<4> M1;
+bits<12> RI2;
+bits<24> RI3;
+let Inst{47-40} = op;
+let Inst{39-36} = M1;
+let Inst{35-24} = RI2;
+let Inst{23-0}  = RI3;
+}
 class InstRIa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 : InstSystemZ<4, outs, ins, asmstr, pattern> {
 field bits<32> Inst;
 field bits<32> SoftFail = 0;
 let Inst{31-16} = I2;
 let Inst{15-8}  = 0;
 let Inst{7-0}   = op{7-0};
 }
+class InstRIEe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+: InstSystemZ<6, outs, ins, asmstr, pattern> {
+field bits<48> Inst;
+field bits<48> SoftFail = 0;
+bits<4> R1;
+bits<4> R3;
+bits<16> RI2;
+let Inst{47-40} = op{15-8};
+let Inst{39-36} = R1;
+let Inst{35-32} = R3;
+let Inst{31-16} = RI2;
+let Inst{15-8}  = 0;
+let Inst{7-0}   = op{7-0};
+}
 class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 : InstSystemZ<6, outs, ins, asmstr, pattern> {
 field bits<48> Inst;
 field bits<48> SoftFail = 0;
 let Inst{11-8}  = 0;
 let Inst{7-4}   = R1;
 let Inst{3-0}   = R2;
 }
+class InstRRFd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+: InstSystemZ<4, outs, ins, asmstr, pattern> {
+field bits<32> Inst;
+field bits<32> SoftFail = 0;
+bits<4> R1;
+bits<4> R2;
+bits<4> M4;
+let Inst{31-16} = op;
+let Inst{15-12} = 0;
+let Inst{11-8}  = M4;
+let Inst{7-4}   = R1;
+let Inst{3-0}   = R2;
+}
 class InstRRFe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 : InstSystemZ<4, outs, ins, asmstr, pattern> {
 field bits<32> Inst;
 field bits<32> SoftFail = 0;
 let Inst{23-20} = R1;
 let Inst{19-16} = R3;
 let Inst{15-0}  = RI2;
 }
+class InstRSLa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+: InstSystemZ<6, outs, ins, asmstr, pattern> {
+field bits<48> Inst;
+field bits<48> SoftFail = 0;
+bits<20> BDL1;
+let Inst{47-40} = op{15-8};
+let Inst{39-36} = BDL1{19-16};
+let Inst{35-32} = 0;
+let Inst{31-16} = BDL1{15-0};
+let Inst{15-8}  = 0;
+let Inst{7-0}   = op{7-0};
+}
+class InstRSLb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+: InstSystemZ<6, outs, ins, asmstr, pattern> {
+field bits<48> Inst;
+field bits<48> SoftFail = 0;
+bits<4> R1;
+bits<24> BDL2;
+bits<4> M3;
+let Inst{47-40} = op{15-8};
+let Inst{39-16} = BDL2;
+let Inst{15-12} = R1;
+let Inst{11-8}  = M3;
+let Inst{7-0}   = op{7-0};
+}
 class InstRSYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 : InstSystemZ<6, outs, ins, asmstr, pattern> {
 field bits<48> Inst;
 field bits<48> SoftFail = 0;
 let Inst{7-0}   = op{7-0};
 let Has20BitOffset = 1;
 }
+class InstSMI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+: InstSystemZ<6, outs, ins, asmstr, pattern> {
+field bits<48> Inst;
+field bits<48> SoftFail = 0;
+bits<4> M1;
+bits<16> RI2;
+bits<16> BD3;
+let Inst{47-40} = op;
+let Inst{39-36} = M1;
+let Inst{35-32} = 0;
+let Inst{31-16} = BD3;
+let Inst{15-0}  = RI2;
+}
 class InstSSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 : InstSystemZ<6, outs, ins, asmstr, pattern> {
 field bits<48> Inst;
 field bits<48> SoftFail = 0;
 bits<24> BDL1;
 bits<16> BD2;
 let Inst{47-40} = op;
 let Inst{39-16} = BDL1;
+let Inst{15-0}  = BD2;
+}
+class InstSSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+: InstSystemZ<6, outs, ins, asmstr, pattern> {
+field bits<48> Inst;
+field bits<48> SoftFail = 0;
+bits<20> BDL1;
+bits<20> BDL2;
+let Inst{47-40} = op;
+let Inst{39-36} = BDL1{19-16};
+let Inst{35-32} = BDL2{19-16};
+let Inst{31-16} = BDL1{15-0};
+let Inst{15-0}  = BDL2{15-0};
+}
+class InstSSc<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+: InstSystemZ<6, outs, ins, asmstr, pattern> {
+field bits<48> Inst;
+field bits<48> SoftFail = 0;
+bits<20> BDL1;
+bits<16> BD2;
+bits<4> I3;
+let Inst{47-40} = op;
+let Inst{39-36} = BDL1{19-16};
+let Inst{35-32} = I3;
+let Inst{31-16} = BDL1{15-0};
 let Inst{15-0}  = BD2;
 }
 class InstSSd<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 : InstSystemZ<6, outs, ins, asmstr, pattern> {
 let Inst{47-40} = op;
 let Inst{39-36} = RBD1{19-16};
 let Inst{35-32} = R3;
 let Inst{31-16} = RBD1{15-0};
 let Inst{15-0}  = BD2;
+}
+class InstSSe<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+: InstSystemZ<6, outs, ins, asmstr, pattern> {
+field bits<48> Inst;
+field bits<48> SoftFail = 0;
+bits<4> R1;
+bits<16> BD2;
+bits<4> R3;
+bits<16> BD4;
+let Inst{47-40} = op;
+let Inst{39-36} = R1;
+let Inst{35-32} = R3;
+let Inst{31-16} = BD2;
+let Inst{15-0}  = BD4;
+}
+class InstSSf<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+: InstSystemZ<6, outs, ins, asmstr, pattern> {
+field bits<48> Inst;
+field bits<48> SoftFail = 0;
+bits<16> BD1;
+bits<24> BDL2;
+let Inst{47-40} = op;
+let Inst{39-32} = BDL2{23-16};
+let Inst{31-16} = BD1;
+let Inst{15-0}  = BDL2{15-0};
 }
 class InstSSE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 : InstSystemZ<6, outs, ins, asmstr, pattern> {
 field bits<48> Inst;
 let Inst{19-16} = M5;
 let Inst{15-12} = M4;
 let Inst{11}    = V1{4};
 let Inst{10}    = V2{4};
 let Inst{9-8}   = 0;
+let Inst{7-0}   = op{7-0};
+}
+class InstVRIf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+: InstSystemZ<6, outs, ins, asmstr, pattern> {
+field bits<48> Inst;
+field bits<48> SoftFail = 0;
+bits<5> V1;
+bits<5> V2;
+bits<5> V3;
+bits<8> I4;
+bits<4> M5;
+let Inst{47-40} = op{15-8};
+let Inst{39-36} = V1{3-0};
+let Inst{35-32} = V2{3-0};
+let Inst{31-28} = V3{3-0};
+let Inst{27-24} = 0;
+let Inst{23-20} = M5;
+let Inst{19-12} = I4;
+let Inst{11}    = V1{4};
+let Inst{10}    = V2{4};
+let Inst{9}     = V3{4};
+let Inst{8}     = 0;
+let Inst{7-0}   = op{7-0};
+}
+class InstVRIg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+: InstSystemZ<6, outs, ins, asmstr, pattern> {
+field bits<48> Inst;
+field bits<48> SoftFail = 0;
+bits<5> V1;
+bits<5> V2;
+bits<8> I3;
+bits<8> I4;
+bits<4> M5;
+let Inst{47-40} = op{15-8};
+let Inst{39-36} = V1{3-0};
+let Inst{35-32} = V2{3-0};
+let Inst{31-24} = I4;
+let Inst{23-20} = M5;
+let Inst{19-12} = I3;
+let Inst{11}    = V1{4};
+let Inst{10}    = V2{4};
+let Inst{9-8}   = 0;
+let Inst{7-0}   = op{7-0};
+}
+class InstVRIh<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+: InstSystemZ<6, outs, ins, asmstr, pattern> {
+field bits<48> Inst;
+field bits<48> SoftFail = 0;
+bits<5> V1;
+bits<16> I2;
+bits<4> I3;
+let Inst{47-40} = op{15-8};
+let Inst{39-36} = V1{3-0};
+let Inst{35-32} = 0;
+let Inst{31-16} = I2;
+let Inst{15-12} = I3;
+let Inst{11}    = V1{4};
+let Inst{10-8}  = 0;
+let Inst{7-0}   = op{7-0};
+}
+class InstVRIi<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+: InstSystemZ<6, outs, ins, asmstr, pattern> {
+field bits<48> Inst;
+field bits<48> SoftFail = 0;
+bits<5> V1;
+bits<4> R2;
+bits<8> I3;
+bits<4> M4;
+let Inst{47-40} = op{15-8};
+let Inst{39-36} = V1{3-0};
+let Inst{35-32} = R2;
+let Inst{31-24} = 0;
+let Inst{23-20} = M4;
+let Inst{19-12} = I3;
+let Inst{11}    = V1{4};
+let Inst{10-8}  = 0;
 let Inst{7-0}   = op{7-0};
 }
 // Depending on the instruction mnemonic, certain bits may be or-ed into
 // the M4 value provided as explicit operand.  These are passed as m4or.
 let Inst{11}    = V1{4};
 let Inst{10-8}  = 0;
 let Inst{7-0}   = op{7-0};
 }
+class InstVRRg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+: InstSystemZ<6, outs, ins, asmstr, pattern> {
+field bits<48> Inst;
+field bits<48> SoftFail = 0;
+bits<5> V1;
+let Inst{47-40} = op{15-8};
+let Inst{39-36} = 0;
+let Inst{35-32} = V1{3-0};
+let Inst{31-12} = 0;
+let Inst{11}    = 0;
+let Inst{10}    = V1{4};
+let Inst{9-8}   = 0;
+let Inst{7-0}   = op{7-0};
+}
+class InstVRRh<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+: InstSystemZ<6, outs, ins, asmstr, pattern> {
+field bits<48> Inst;
+field bits<48> SoftFail = 0;
+bits<5> V1;
+bits<5> V2;
+bits<4> M3;
+let Inst{47-40} = op{15-8};
+let Inst{39-36} = 0;
+let Inst{35-32} = V1{3-0};
+let Inst{31-28} = V2{3-0};
+let Inst{27-24} = 0;
+let Inst{23-20} = M3;
+let Inst{19-12} = 0;
+let Inst{11}    = 0;
+let Inst{10}    = V1{4};
+let Inst{9}     = V2{4};
+let Inst{8}     = 0;
+let Inst{7-0}   = op{7-0};
+}
+class InstVRRi<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+: InstSystemZ<6, outs, ins, asmstr, pattern> {
+field bits<48> Inst;
+field bits<48> SoftFail = 0;
+bits<4> R1;
+bits<5> V2;
+bits<4> M3;
+let Inst{47-40} = op{15-8};
+let Inst{39-36} = R1;
+let Inst{35-32} = V2{3-0};
+let Inst{31-24} = 0;
+let Inst{23-20} = M3;
+let Inst{19-12} = 0;
+let Inst{11}    = 0;
+let Inst{10}    = V2{4};
+let Inst{9-8}   = 0;
+let Inst{7-0}   = op{7-0};
+}
 class InstVRSa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 : InstSystemZ<6, outs, ins, asmstr, pattern> {
 field bits<48> Inst;
 field bits<48> SoftFail = 0;
 let Inst{10}    = V3{4};
 let Inst{9-8}   = 0;
 let Inst{7-0}   = op{7-0};
 }
+class InstVRSd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+: InstSystemZ<6, outs, ins, asmstr, pattern> {
+field bits<48> Inst;
+field bits<48> SoftFail = 0;
+bits<5> V1;
+bits<16> BD2;
+bits<4> R3;
+let Inst{47-40} = op{15-8};
+let Inst{39-36} = 0;
+let Inst{35-32} = R3;
+let Inst{31-16} = BD2;
+let Inst{15-12} = V1{3-0};
+let Inst{11-9}  = 0;
+let Inst{8}     = V1{4};
+let Inst{7-0}   = op{7-0};
+}
 class InstVRV<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 : InstSystemZ<6, outs, ins, asmstr, pattern> {
 field bits<48> Inst;
 field bits<48> SoftFail = 0;
 let Inst{39-36} = V1{3-0};
 let Inst{35-16} = XBD2;
 let Inst{15-12} = M3;
 let Inst{11}    = V1{4};
 let Inst{10-8}  = 0;
+let Inst{7-0}   = op{7-0};
+}
+class InstVSI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+: InstSystemZ<6, outs, ins, asmstr, pattern> {
+field bits<48> Inst;
+field bits<48> SoftFail = 0;
+bits<5> V1;
+bits<16> BD2;
+bits<8> I3;
+let Inst{47-40} = op{15-8};
+let Inst{39-32} = I3;
+let Inst{31-16} = BD2;
+let Inst{15-12} = V1{3-0};
+let Inst{11-9}  = 0;
+let Inst{8}     = V1{4};
 let Inst{7-0}   = op{7-0};
 }
 //===----------------------------------------------------------------------===//
 // Instruction classes for .insn directives
 // <Category> can be one of:
 //
 //   Inherent:
 //     One register output operand and no input operands.
 //
+//   InherentDual:
+//     Two register output operands and no input operands.
+//
 //   StoreInherent:
 //     One address operand.  The instruction stores to the address.
 //
 //   SideEffectInherent:
 //     No input or output operands, but causes some side effect.
 //   CmpBranch:
 //     Two input operands and one optional branch target.  The instruction
 //     compares the two input operands and branches or traps on the result.
 //
 //   BranchUnary:
-//     One register output operand, one register input operand and
+//     One register output operand, one register input operand and one branch
-//     one branch displacement.  The instructions stores a modified
+//     target.  The instructions stores a modified form of the source register
-//     form of the source register in the destination register and
+//     in the destination register and branches on the result.
-//     branches on the result.
 //
 //   BranchBinary:
 //     One register output operand, two register input operands and one branch
-//     displacement. The instructions stores a modified form of one of the
+//     target. The instructions stores a modified form of one of the source
-//     source registers in the destination register and branches on the result.
+//     registers in the destination register and branches on the result.
 //
 //   LoadMultiple:
 //     One address input operand and two explicit output operands.
 //     The instruction loads a range of registers from the address,
 //     with the explicit operands giving the first and last register
 //     length operand.
 //
 //   LoadAddress:
 //     One register output operand and one address operand.
 //
+//   SideEffectAddress:
+//     One address operand.  No output operands, but causes some side effect.
+//
 //   Unary:
 //     One register output operand and one input operand.
 //
 //   Store:
 //     One address operand and one other input operand.  The instruction
 //
 //   Compare:
 //     Two input operands and an implicit CC output operand.
 //
 //   Test:
-//     Two input operands and an implicit CC output operand.  The second
+//     One or two input operands and an implicit CC output operand.  If
-//     input operand is an "address" operand used as a test class mask.
+//     present, the second input operand is an "address" operand used as
+//     a test class mask.
 //
 //   Ternary:
 //     One register output operand and three input operands.
 //
 //   SideEffectTernary:
 //     are registers and the other three are immediates.
 //
 //   Prefetch:
 //     One 4-bit immediate operand and one address operand.  The immediate
 //     operand is 1 for a load prefetch and 2 for a store prefetch.
+//
+//   BranchPreload:
+//     One 4-bit immediate operand and two address operands.
 //
 // The format determines which input operands are tied to output operands,
 // and also determines the shape of any address operand.
 //
 // Multiclasses of the form <Category><Format>Pair define two instructions,
 mnemonic#"\t$R1",
 [(set cls:$R1, (operator))]> {
 let R2 = 0;
 }
+class InherentDualRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
+: InstRRE<opcode, (outs cls:$R1, cls:$R2), (ins),
+mnemonic#"\t$R1, $R2", []>;
 class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value>
 : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
 let I2 = value;
 let M3 = 0;
 }
-class StoreInherentS<string mnemonic, bits<16> opcode>
+class StoreInherentS<string mnemonic, bits<16> opcode,
+SDPatternOperator operator, bits<5> bytes>
 : InstS<opcode, (outs), (ins bdaddr12only:$BD2),
-mnemonic#"\t$BD2", []> {
+mnemonic#"\t$BD2", [(operator bdaddr12only:$BD2)]> {
 let mayStore = 1;
+let AccessBytes = bytes;
 }
 class SideEffectInherentE<string mnemonic, bits<16>opcode>
-: InstE<opcode, (outs), (ins), mnemonic, []> {
+: InstE<opcode, (outs), (ins), mnemonic, []>;
-let hasSideEffects = 1;
-}
 class SideEffectInherentS<string mnemonic, bits<16> opcode,
 SDPatternOperator operator>
 : InstS<opcode, (outs), (ins), mnemonic, [(operator)]> {
-let hasSideEffects = 1;
 let BD2 = 0;
+}
+class SideEffectInherentRRE<string mnemonic, bits<16> opcode>
+: InstRRE<opcode, (outs), (ins), mnemonic, []> {
+let R1 = 0;
+let R2 = 0;
 }
 // Allow an optional TLS marker symbol to generate TLS call relocations.
 class CallRI<string mnemonic, bits<12> opcode>
 : InstRIb<opcode, (outs), (ins GR64:$R1, brtarget16tls:$RI2),
 !subst("#", V.suffix, mnemonic)#"\t$XBD2", []> {
 let isAsmParserOnly = V.alternate;
 let M1 = V.ccmask;
 }
+class CondBranchRXY<string mnemonic, bits<16> opcode>
+: InstRXYb<opcode, (outs), (ins cond4:$valid, cond4:$M1, bdxaddr20only:$XBD2),
+!subst("#", "${M1}", mnemonic)#"\t$XBD2", []> {
+let CCMaskFirst = 1;
+}
+class AsmCondBranchRXY<string mnemonic, bits<16> opcode>
+: InstRXYb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr20only:$XBD2),
+mnemonic#"\t$M1, $XBD2", []>;
+class FixedCondBranchRXY<CondVariant V, string mnemonic, bits<16> opcode,
+SDPatternOperator operator = null_frag>
+: InstRXYb<opcode, (outs), (ins bdxaddr20only:$XBD2),
+!subst("#", V.suffix, mnemonic)#"\t$XBD2",
+[(operator (load bdxaddr20only:$XBD2))]> {
+let isAsmParserOnly = V.alternate;
+let M1 = V.ccmask;
+}
 class CmpBranchRIEa<string mnemonic, bits<16> opcode,
 RegisterOperand cls, Immediate imm>
 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, cond4:$M3),
 mnemonic#"$M3\t$R1, $I2", []>;
 mnemonic##"\t$R1, $RI2", []> {
 let Constraints = "$R1 = $R1src";
 let DisableEncoding = "$R1src";
 }
+class BranchUnaryRIL<string mnemonic, bits<12> opcode, RegisterOperand cls>
+: InstRILb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget32:$RI2),
+mnemonic##"\t$R1, $RI2", []> {
+let Constraints = "$R1 = $R1src";
+let DisableEncoding = "$R1src";
+}
+class BranchUnaryRR<string mnemonic, bits<8> opcode, RegisterOperand cls>
+: InstRR<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2),
+mnemonic##"\t$R1, $R2", []> {
+let Constraints = "$R1 = $R1src";
+let DisableEncoding = "$R1src";
+}
+class BranchUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
+: InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2),
+mnemonic##"\t$R1, $R2", []> {
+let Constraints = "$R1 = $R1src";
+let DisableEncoding = "$R1src";
+}
+class BranchUnaryRX<string mnemonic, bits<8> opcode, RegisterOperand cls>
+: InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
+mnemonic##"\t$R1, $XBD2", []> {
+let Constraints = "$R1 = $R1src";
+let DisableEncoding = "$R1src";
+}
+class BranchUnaryRXY<string mnemonic, bits<16> opcode, RegisterOperand cls>
+: InstRXYa<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr20only:$XBD2),
+mnemonic##"\t$R1, $XBD2", []> {
+let Constraints = "$R1 = $R1src";
+let DisableEncoding = "$R1src";
+}
 class BranchBinaryRSI<string mnemonic, bits<8> opcode, RegisterOperand cls>
 : InstRSI<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, brtarget16:$RI2),
 mnemonic##"\t$R1, $R3, $RI2", []> {
+let Constraints = "$R1 = $R1src";
+let DisableEncoding = "$R1src";
+}
+class BranchBinaryRIEe<string mnemonic, bits<16> opcode, RegisterOperand cls>
+: InstRIEe<opcode, (outs cls:$R1),
+(ins cls:$R1src, cls:$R3, brtarget16:$RI2),
+mnemonic##"\t$R1, $R3, $RI2", []> {
+let Constraints = "$R1 = $R1src";
+let DisableEncoding = "$R1src";
+}
+class BranchBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls>
+: InstRSa<opcode, (outs cls:$R1),
+(ins cls:$R1src, cls:$R3, bdaddr12only:$BD2),
+mnemonic##"\t$R1, $R3, $BD2", []> {
+let Constraints = "$R1 = $R1src";
+let DisableEncoding = "$R1src";
+}
+class BranchBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
+: InstRSYa<opcode,
+(outs cls:$R1), (ins cls:$R1src, cls:$R3, bdaddr20only:$BD2),
+mnemonic##"\t$R1, $R3, $BD2", []> {
 let Constraints = "$R1 = $R1src";
 let DisableEncoding = "$R1src";
 }
 class LoadMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
 let DispSize = "12" in
 def "" : LoadMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
 let DispSize = "20" in
 def Y  : LoadMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
 }
+}
+class LoadMultipleSSe<string mnemonic, bits<8> opcode, RegisterOperand cls>
+: InstSSe<opcode, (outs cls:$R1, cls:$R3),
+(ins bdaddr12only:$BD2, bdaddr12only:$BD4),
+mnemonic#"\t$R1, $R3, $BD2, $BD4", []> {
+let mayLoad = 1;
 }
 class LoadMultipleVRSa<string mnemonic, bits<16> opcode>
 : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3), (ins bdaddr12only:$BD2),
 mnemonic#"\t$V1, $V3, $BD2", []> {
 SDPatternOperator operator, bits<5> bytes>
 : InstVRSb<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
 mnemonic#"\t$V1, $R3, $BD2",
 [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
 let M4 = 0;
+let mayStore = 1;
+let AccessBytes = bytes;
+}
+class StoreLengthVRSd<string mnemonic, bits<16> opcode,
+SDPatternOperator operator, bits<5> bytes>
+: InstVRSd<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
+mnemonic#"\t$V1, $R3, $BD2",
+[(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
+let mayStore = 1;
+let AccessBytes = bytes;
+}
+class StoreLengthVSI<string mnemonic, bits<16> opcode,
+SDPatternOperator operator, bits<5> bytes>
+: InstVSI<opcode, (outs), (ins VR128:$V1, bdaddr12only:$BD2, imm32zx8:$I3),
+mnemonic#"\t$V1, $BD2, $I3",
+[(operator VR128:$V1, imm32zx8:$I3, bdaddr12only:$BD2)]> {
 let mayStore = 1;
 let AccessBytes = bytes;
 }
 class StoreMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
 def Asm : AsmCondStoreRSY<mnemonic, opcode, cls, bytes, mode>;
 }
 class SideEffectUnaryI<string mnemonic, bits<8> opcode, Immediate imm>
 : InstI<opcode, (outs), (ins imm:$I1),
-mnemonic#"\t$I1", []> {
+mnemonic#"\t$I1", []>;
-let hasSideEffects = 1;
-}
 class SideEffectUnaryRR<string mnemonic, bits<8>opcode, RegisterOperand cls>
 : InstRR<opcode, (outs), (ins cls:$R1),
 mnemonic#"\t$R1", []> {
-let hasSideEffects = 1;
 let R2 = 0;
 }
+class SideEffectUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
+SDPatternOperator operator>
+: InstRRE<opcode, (outs), (ins cls:$R1),
+mnemonic#"\t$R1", [(operator cls:$R1)]> {
+let R2 = 0;
+}
 class SideEffectUnaryS<string mnemonic, bits<16> opcode,
-SDPatternOperator operator>
+SDPatternOperator operator, bits<5> bytes,
-: InstS<opcode, (outs), (ins bdaddr12only:$BD2),
+AddressingMode mode = bdaddr12only>
-mnemonic#"\t$BD2", [(operator bdaddr12only:$BD2)]> {
+: InstS<opcode, (outs), (ins mode:$BD2),
-let hasSideEffects = 1;
+mnemonic#"\t$BD2", [(operator mode:$BD2)]> {
-}
+let mayLoad = 1;
+let AccessBytes = bytes;
+}
+class SideEffectAddressS<string mnemonic, bits<16> opcode,
+SDPatternOperator operator,
+AddressingMode mode = bdaddr12only>
+: InstS<opcode, (outs), (ins mode:$BD2),
+mnemonic#"\t$BD2", [(operator mode:$BD2)]>;
 class LoadAddressRX<string mnemonic, bits<8> opcode,
 SDPatternOperator operator, AddressingMode mode>
 : InstRXa<opcode, (outs GR64:$R1), (ins mode:$XBD2),
 mnemonic#"\t$R1, $XBD2",
 [(set cls1:$R1, (operator cls2:$R2))]> {
 let OpKey = mnemonic#cls1;
 let OpType = "reg";
 }
-// These instructions are generated by if conversion.  The old value of R1
+class UnaryTiedRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
-// is added as an implicit use.
+: InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src),
-class CondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
+mnemonic#"\t$R1", []> {
-RegisterOperand cls2>
-: InstRRFc<opcode, (outs cls1:$R1), (ins cls2:$R2, cond4:$valid, cond4:$M3),
-mnemonic#"$M3\t$R1, $R2", []> {
-let CCMaskLast = 1;
-}
-class CondUnaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
-Immediate imm>
-: InstRIEg<opcode, (outs cls:$R1), (ins imm:$I2, cond4:$valid, cond4:$M3),
-mnemonic#"$M3\t$R1, $I2", []> {
-let CCMaskLast = 1;
-}
-// Like CondUnaryRRF, but used for the raw assembly form.  The condition-code
-// mask is the third operand rather than being part of the mnemonic.
-class AsmCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
-RegisterOperand cls2>
-: InstRRFc<opcode, (outs cls1:$R1),
-(ins cls1:$R1src, cls2:$R2, imm32zx4:$M3),
-mnemonic#"\t$R1, $R2, $M3", []> {
 let Constraints = "$R1 = $R1src";
 let DisableEncoding = "$R1src";
-}
+let R2 = 0;
+}
-class AsmCondUnaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
-Immediate imm>
+class UnaryMemRRFc<string mnemonic, bits<16> opcode,
-: InstRIEg<opcode, (outs cls:$R1),
+RegisterOperand cls1, RegisterOperand cls2>
-(ins cls:$R1src, imm:$I2, imm32zx4:$M3),
+: InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src),
-mnemonic#"\t$R1, $I2, $M3", []> {
+mnemonic#"\t$R1, $R2", []> {
 let Constraints = "$R1 = $R1src";
 let DisableEncoding = "$R1src";
-}
+let M3 = 0;
-// Like CondUnaryRRF, but with a fixed CC mask.
-class FixedCondUnaryRRF<CondVariant V, string mnemonic, bits<16> opcode,
-RegisterOperand cls1, RegisterOperand cls2>
-: InstRRFc<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
-mnemonic#V.suffix#"\t$R1, $R2", []> {
-let Constraints = "$R1 = $R1src";
-let DisableEncoding = "$R1src";
-let isAsmParserOnly = V.alternate;
-let M3 = V.ccmask;
-}
-class FixedCondUnaryRIE<CondVariant V, string mnemonic, bits<16> opcode,
-RegisterOperand cls, Immediate imm>
-: InstRIEg<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
-mnemonic#V.suffix#"\t$R1, $I2", []> {
-let Constraints = "$R1 = $R1src";
-let DisableEncoding = "$R1src";
-let isAsmParserOnly = V.alternate;
-let M3 = V.ccmask;
-}
-multiclass CondUnaryRRFPair<string mnemonic, bits<16> opcode,
-RegisterOperand cls1, RegisterOperand cls2> {
-let isCodeGenOnly = 1 in
-def "" : CondUnaryRRF<mnemonic, opcode, cls1, cls2>;
-def Asm : AsmCondUnaryRRF<mnemonic, opcode, cls1, cls2>;
-}
-multiclass CondUnaryRIEPair<string mnemonic, bits<16> opcode,
-RegisterOperand cls, Immediate imm> {
-let isCodeGenOnly = 1 in
-def "" : CondUnaryRIE<mnemonic, opcode, cls, imm>;
-def Asm : AsmCondUnaryRIE<mnemonic, opcode, cls, imm>;
 }
 class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
 RegisterOperand cls, Immediate imm>
 : InstRIa<opcode, (outs cls:$R1), (ins imm:$I2),
 }
 class SideEffectBinaryRX<string mnemonic, bits<8> opcode,
 RegisterOperand cls>
 : InstRXa<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
-mnemonic##"\t$R1, $XBD2", []> {
+mnemonic##"\t$R1, $XBD2", []>;
-let hasSideEffects = 1;
-}
+class SideEffectBinaryRXY<string mnemonic, bits<16> opcode,
+RegisterOperand cls>
+: InstRXYa<opcode, (outs), (ins cls:$R1, bdxaddr20only:$XBD2),
+mnemonic##"\t$R1, $XBD2", []>;
 class SideEffectBinaryRILPC<string mnemonic, bits<12> opcode,
 RegisterOperand cls>
 : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
 mnemonic##"\t$R1, $RI2", []> {
-let hasSideEffects = 1;
 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
 // However, BDXs have two extra operands and are therefore 6 units more
 // complex.
 let AddedComplexity = 7;
 }
+class SideEffectBinaryRRE<string mnemonic, bits<16> opcode,
+RegisterOperand cls1, RegisterOperand cls2>
+: InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
+mnemonic#"\t$R1, $R2", []>;
+class SideEffectBinaryRRFa<string mnemonic, bits<16> opcode,
+RegisterOperand cls1, RegisterOperand cls2>
+: InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2),
+mnemonic#"\t$R1, $R2", []> {
+let R3 = 0;
+let M4 = 0;
+}
+class SideEffectBinaryRRFc<string mnemonic, bits<16> opcode,
+RegisterOperand cls1, RegisterOperand cls2>
+: InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2),
+mnemonic#"\t$R1, $R2", []> {
+let M3 = 0;
+}
+class SideEffectBinaryIE<string mnemonic, bits<16> opcode,
+Immediate imm1, Immediate imm2>
+: InstIE<opcode, (outs), (ins imm1:$I1, imm2:$I2),
+mnemonic#"\t$I1, $I2", []>;
+class SideEffectBinarySI<string mnemonic, bits<8> opcode, Operand imm>
+: InstSI<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
+mnemonic#"\t$BD1, $I2", []>;
 class SideEffectBinarySIL<string mnemonic, bits<16> opcode,
 SDPatternOperator operator, Immediate imm>
 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
-mnemonic#"\t$BD1, $I2", [(operator bdaddr12only:$BD1, imm:$I2)]> {
+mnemonic#"\t$BD1, $I2", [(operator bdaddr12only:$BD1, imm:$I2)]>;
-let hasSideEffects = 1;
+class SideEffectBinarySSa<string mnemonic, bits<8> opcode>
+: InstSSa<opcode, (outs), (ins bdladdr12onlylen8:$BDL1, bdaddr12only:$BD2),
+mnemonic##"\t$BDL1, $BD2", []>;
+class SideEffectBinarySSb<string mnemonic, bits<8> opcode>
+: InstSSb<opcode,
+(outs), (ins bdladdr12onlylen4:$BDL1, bdladdr12onlylen4:$BDL2),
+mnemonic##"\t$BDL1, $BDL2", []>;
+class SideEffectBinarySSf<string mnemonic, bits<8> opcode>
+: InstSSf<opcode, (outs), (ins bdaddr12only:$BD1, bdladdr12onlylen8:$BDL2),
+mnemonic##"\t$BD1, $BDL2", []>;
+class SideEffectBinarySSE<string mnemonic, bits<16> opcode>
+: InstSSE<opcode, (outs), (ins bdaddr12only:$BD1, bdaddr12only:$BD2),
+mnemonic#"\t$BD1, $BD2", []>;
+class SideEffectBinaryMemMemRR<string mnemonic, bits<8> opcode,
+RegisterOperand cls1, RegisterOperand cls2>
+: InstRR<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
+mnemonic#"\t$R1, $R2", []> {
+let Constraints = "$R1 = $R1src, $R2 = $R2src";
+let DisableEncoding = "$R1src, $R2src";
+}
+class SideEffectBinaryMemRRE<string mnemonic, bits<16> opcode,
+RegisterOperand cls1, RegisterOperand cls2>
+: InstRRE<opcode, (outs cls2:$R2), (ins cls1:$R1, cls2:$R2src),
+mnemonic#"\t$R1, $R2", []> {
+let Constraints = "$R2 = $R2src";
+let DisableEncoding = "$R2src";
+}
+class SideEffectBinaryMemMemRRE<string mnemonic, bits<16> opcode,
+RegisterOperand cls1, RegisterOperand cls2>
+: InstRRE<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
+mnemonic#"\t$R1, $R2", []> {
+let Constraints = "$R1 = $R1src, $R2 = $R2src";
+let DisableEncoding = "$R1src, $R2src";
+}
+class SideEffectBinaryMemMemRRFc<string mnemonic, bits<16> opcode,
+RegisterOperand cls1, RegisterOperand cls2>
+: InstRRFc<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
+mnemonic#"\t$R1, $R2", []> {
+let Constraints = "$R1 = $R1src, $R2 = $R2src";
+let DisableEncoding = "$R1src, $R2src";
+let M3 = 0;
 }
 class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
 RegisterOperand cls1, RegisterOperand cls2>
 : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
 let OpKey = mnemonic#cls1;
 let OpType = "reg";
 let Constraints = "$R1 = $R1src";
 let DisableEncoding = "$R1src";
+}
+class BinaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator,
+RegisterOperand cls1, RegisterOperand cls2>
+: InstRRD<opcode, (outs cls1:$R1), (ins cls2:$R3, cls2:$R2),
+mnemonic#"\t$R1, $R3, $R2",
+[(set cls1:$R1, (operator cls2:$R3, cls2:$R2))]> {
+let OpKey = mnemonic#cls;
+let OpType = "reg";
 }
 class BinaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
 RegisterOperand cls1, RegisterOperand cls2,
 RegisterOperand cls3>
 mnemonic#"\t$R1, $R3, $R2",
 [(set cls1:$R1, (operator cls2:$R2, cls3:$R3))]> {
 let M4 = 0;
 }
+class BinaryMemRRFc<string mnemonic, bits<16> opcode,
+RegisterOperand cls1, RegisterOperand cls2, Immediate imm>
+: InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src, imm:$M3),
+mnemonic#"\t$R1, $R2, $M3", []> {
+let Constraints = "$R1 = $R1src";
+let DisableEncoding = "$R1src";
+}
+multiclass BinaryMemRRFcOpt<string mnemonic, bits<16> opcode,
+RegisterOperand cls1, RegisterOperand cls2> {
+def "" : BinaryMemRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
+def Opt : UnaryMemRRFc<mnemonic, opcode, cls1, cls2>;
+}
+class BinaryRRFd<string mnemonic, bits<16> opcode, RegisterOperand cls1,
+RegisterOperand cls2>
+: InstRRFd<opcode, (outs cls1:$R1), (ins cls2:$R2, imm32zx4:$M4),
+mnemonic#"\t$R1, $R2, $M4", []>;
 class BinaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
 RegisterOperand cls2>
 : InstRRFe<opcode, (outs cls1:$R1), (ins imm32zx4:$M3, cls2:$R2),
 mnemonic#"\t$R1, $M3, $R2", []> {
 let M4 = 0;
+}
+class CondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
+RegisterOperand cls2>
+: InstRRFc<opcode, (outs cls1:$R1),
+(ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3),
+mnemonic#"$M3\t$R1, $R2", []> {
+let Constraints = "$R1 = $R1src";
+let DisableEncoding = "$R1src";
+let CCMaskLast = 1;
+}
+// Like CondBinaryRRF, but used for the raw assembly form.  The condition-code
+// mask is the third operand rather than being part of the mnemonic.
+class AsmCondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
+RegisterOperand cls2>
+: InstRRFc<opcode, (outs cls1:$R1),
+(ins cls1:$R1src, cls2:$R2, imm32zx4:$M3),
+mnemonic#"\t$R1, $R2, $M3", []> {
+let Constraints = "$R1 = $R1src";
+let DisableEncoding = "$R1src";
+}
+// Like CondBinaryRRF, but with a fixed CC mask.
+class FixedCondBinaryRRF<CondVariant V, string mnemonic, bits<16> opcode,
+RegisterOperand cls1, RegisterOperand cls2>
+: InstRRFc<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
+mnemonic#V.suffix#"\t$R1, $R2", []> {
+let Constraints = "$R1 = $R1src";
+let DisableEncoding = "$R1src";
+let isAsmParserOnly = V.alternate;
+let M3 = V.ccmask;
+}
+multiclass CondBinaryRRFPair<string mnemonic, bits<16> opcode,
+RegisterOperand cls1, RegisterOperand cls2> {
+let isCodeGenOnly = 1 in
+def "" : CondBinaryRRF<mnemonic, opcode, cls1, cls2>;
+def Asm : AsmCondBinaryRRF<mnemonic, opcode, cls1, cls2>;
 }
 class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
 RegisterOperand cls, Immediate imm>
 : InstRIa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
 def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>;
 }
 }
+class CondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
+Immediate imm>
+: InstRIEg<opcode, (outs cls:$R1),
+(ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
+mnemonic#"$M3\t$R1, $I2",
+[(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src,
+cond4:$valid, cond4:$M3))]> {
+let Constraints = "$R1 = $R1src";
+let DisableEncoding = "$R1src";
+let CCMaskLast = 1;
+}
+// Like CondBinaryRIE, but used for the raw assembly form.  The condition-code
+// mask is the third operand rather than being part of the mnemonic.
+class AsmCondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
+Immediate imm>
+: InstRIEg<opcode, (outs cls:$R1),
+(ins cls:$R1src, imm:$I2, imm32zx4:$M3),
+mnemonic#"\t$R1, $I2, $M3", []> {
+let Constraints = "$R1 = $R1src";
+let DisableEncoding = "$R1src";
+}
+// Like CondBinaryRIE, but with a fixed CC mask.
+class FixedCondBinaryRIE<CondVariant V, string mnemonic, bits<16> opcode,
+RegisterOperand cls, Immediate imm>
+: InstRIEg<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
+mnemonic#V.suffix#"\t$R1, $I2", []> {
+let Constraints = "$R1 = $R1src";
+let DisableEncoding = "$R1src";
+let isAsmParserOnly = V.alternate;
+let M3 = V.ccmask;
+}
+multiclass CondBinaryRIEPair<string mnemonic, bits<16> opcode,
+RegisterOperand cls, Immediate imm> {
+let isCodeGenOnly = 1 in
+def "" : CondBinaryRIE<mnemonic, opcode, cls, imm>;
+def Asm : AsmCondBinaryRIE<mnemonic, opcode, cls, imm>;
+}
 class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
 RegisterOperand cls, Immediate imm>
 : InstRILa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
 mnemonic#"\t$R1, $I2",
 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
 def K  : BinaryRSY<mnemonic##"k", opcode2, null_frag, cls>,
 Requires<[FeatureDistinctOps]>;
 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
 def "" : BinaryRS<mnemonic, opcode1, operator, cls>;
 }
+}
+class BinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls>
+: InstRSLb<opcode, (outs cls:$R1),
+(ins bdladdr12onlylen8:$BDL2, imm32zx4:$M3),
+mnemonic#"\t$R1, $BDL2, $M3", []> {
+let mayLoad = 1;
 }
 class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
 AddressingMode mode = bdxaddr12only>
 let Constraints = "$R1 = $R1src";
 let DisableEncoding = "$R1src";
 let mayLoad = 1;
 let AccessBytes = bytes;
 let M3 = 0;
+}
+class BinaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
+RegisterOperand cls1, RegisterOperand cls2,
+SDPatternOperator load, bits<5> bytes>
+: InstRXF<opcode, (outs cls1:$R1), (ins cls2:$R3, bdxaddr12only:$XBD2),
+mnemonic#"\t$R1, $R3, $XBD2",
+[(set cls1:$R1, (operator cls2:$R3, (load bdxaddr12only:$XBD2)))]> {
+let OpKey = mnemonic#"r"#cls;
+let OpType = "mem";
+let mayLoad = 1;
+let AccessBytes = bytes;
 }
 class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
 AddressingMode mode = bdxaddr20only>
 let DispSize = "20" in
 def Y  : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>;
 }
 }
+class BinarySSF<string mnemonic, bits<12> opcode, RegisterOperand cls>
+: InstSSF<opcode, (outs cls:$R3), (ins bdaddr12pair:$BD1, bdaddr12pair:$BD2),
+mnemonic#"\t$R3, $BD1, $BD2", []> {
+let mayLoad = 1;
+}
 class BinaryVRIb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
 TypedReg tr, bits<4> type>
 : InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3),
 mnemonic#"\t$V1, $I2, $I3",
 [(set tr.op:$V1, (tr.vt (operator imm32zx8:$I2, imm32zx8:$I3)))]> {
 class BinaryVRIeFloatGeneric<string mnemonic, bits<16> opcode>
 : InstVRIe<opcode, (outs VR128:$V1),
 (ins VR128:$V2, imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5),
 mnemonic#"\t$V1, $V2, $I3, $M4, $M5", []>;
+class BinaryVRIh<string mnemonic, bits<16> opcode>
+: InstVRIh<opcode, (outs VR128:$V1),
+(ins imm32zx16:$I2, imm32zx4:$I3),
+mnemonic#"\t$V1, $I2, $I3", []>;
 class BinaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0>
 : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx4:$M5),
 mnemonic#"\t$V1, $V2, $M5",
 TypedReg tr>
 : InstVRRf<opcode, (outs tr.op:$V1), (ins GR64:$R2, GR64:$R3),
 mnemonic#"\t$V1, $R2, $R3",
 [(set tr.op:$V1, (tr.vt (operator GR64:$R2, GR64:$R3)))]>;
+class BinaryVRRi<string mnemonic, bits<16> opcode, RegisterOperand cls>
+: InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2, imm32zx4:$M3),
+mnemonic#"\t$R1, $V2, $M3", []>;
 class BinaryVRSa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
 TypedReg tr1, TypedReg tr2, bits<4> type>
 : InstVRSa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, shift12only:$BD2),
 mnemonic#"\t$V1, $V3, $BD2",
 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
 class BinaryVRScGeneric<string mnemonic, bits<16> opcode>
 : InstVRSc<opcode, (outs GR64:$R1),
 (ins VR128:$V3, shift12only:$BD2, imm32zx4: $M4),
 mnemonic#"\t$R1, $V3, $BD2, $M4", []>;
+class BinaryVRSd<string mnemonic, bits<16> opcode, SDPatternOperator operator,
+bits<5> bytes>
+: InstVRSd<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2),
+mnemonic#"\t$V1, $R3, $BD2",
+[(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
+let mayLoad = 1;
+let AccessBytes = bytes;
+}
 class BinaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
 TypedReg tr, bits<5> bytes>
 : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
 mnemonic#"\t$V1, $XBD2, $M3",
 [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2,
 imm32zx4:$M3)))]> {
+let mayLoad = 1;
+let AccessBytes = bytes;
+}
+class StoreBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
+bits<5> bytes, AddressingMode mode = bdaddr12only>
+: InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
+mnemonic#"\t$R1, $M3, $BD2", []> {
+let mayStore = 1;
+let AccessBytes = bytes;
+}
+class StoreBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
+bits<5> bytes, AddressingMode mode = bdaddr20only>
+: InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
+mnemonic#"\t$R1, $M3, $BD2", []> {
+let mayStore = 1;
+let AccessBytes = bytes;
+}
+multiclass StoreBinaryRSPair<string mnemonic, bits<8> rsOpcode,
+bits<16> rsyOpcode, RegisterOperand cls,
+bits<5> bytes> {
+let DispKey = mnemonic ## #cls in {
+let DispSize = "12" in
+def "" : StoreBinaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
+let DispSize = "20" in
+def Y  : StoreBinaryRSY<mnemonic#"y", rsyOpcode, cls, bytes,
+bdaddr20pair>;
+}
+}
+class StoreBinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls>
+: InstRSLb<opcode, (outs),
+(ins cls:$R1, bdladdr12onlylen8:$BDL2, imm32zx4:$M3),
+mnemonic#"\t$R1, $BDL2, $M3", []> {
+let mayStore = 1;
+}
+class BinaryVSI<string mnemonic, bits<16> opcode, SDPatternOperator operator,
+bits<5> bytes>
+: InstVSI<opcode, (outs VR128:$V1), (ins bdaddr12only:$BD2, imm32zx8:$I3),
+mnemonic#"\t$V1, $BD2, $I3",
+[(set VR128:$V1, (operator imm32zx8:$I3, bdaddr12only:$BD2))]> {
 let mayLoad = 1;
 let AccessBytes = bytes;
 }
 class StoreBinaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
 def Y  : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls,
 load, bytes, bdxaddr20pair>;
 }
 }
+class CompareRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
+bits<5> bytes, AddressingMode mode = bdaddr12only>
+: InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
+mnemonic#"\t$R1, $M3, $BD2", []> {
+let mayLoad = 1;
+let AccessBytes = bytes;
+}
+class CompareRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
+bits<5> bytes, AddressingMode mode = bdaddr20only>
+: InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
+mnemonic#"\t$R1, $M3, $BD2", []> {
+let mayLoad = 1;
+let AccessBytes = bytes;
+}
+multiclass CompareRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
+RegisterOperand cls, bits<5> bytes> {
+let DispKey = mnemonic ## #cls in {
+let DispSize = "12" in
+def "" : CompareRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
+let DispSize = "20" in
+def Y  : CompareRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>;
+}
+}
+class CompareSSb<string mnemonic, bits<8> opcode>
+: InstSSb<opcode,
+(outs), (ins bdladdr12onlylen4:$BDL1, bdladdr12onlylen4:$BDL2),
+mnemonic##"\t$BDL1, $BDL2", []> {
+let isCompare = 1;
+let mayLoad = 1;
+}
 class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
 SDPatternOperator load, Immediate imm,
 AddressingMode mode = bdaddr12only>
 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
 mnemonic#"\t$BD1, $I2",
 mnemonic#"\t$V1, $V2, $M3, $M4", []> {
 let isCompare = 1;
 let M5 = 0;
 }
+class CompareVRRh<string mnemonic, bits<16> opcode>
+: InstVRRh<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
+mnemonic#"\t$V1, $V2, $M3", []> {
+let isCompare = 1;
+}
 class TestRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
 RegisterOperand cls>
 : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
 mnemonic#"\t$R1, $XBD2",
 [(operator cls:$R1, bdxaddr12only:$XBD2)]> {
 let M3 = 0;
 }
+class TestRSL<string mnemonic, bits<16> opcode>
+: InstRSLa<opcode, (outs), (ins bdladdr12onlylen4:$BDL1),
+mnemonic#"\t$BDL1", []> {
+let mayLoad = 1;
+}
+class TestVRRg<string mnemonic, bits<16> opcode>
+: InstVRRg<opcode, (outs), (ins VR128:$V1),
+mnemonic#"\t$V1", []>;
+class SideEffectTernarySSc<string mnemonic, bits<8> opcode>
+: InstSSc<opcode, (outs), (ins bdladdr12onlylen4:$BDL1,
+shift12only:$BD2, imm32zx4:$I3),
+mnemonic##"\t$BDL1, $BD2, $I3", []>;
+class SideEffectTernaryRRFa<string mnemonic, bits<16> opcode,
+RegisterOperand cls1, RegisterOperand cls2,
+RegisterOperand cls3>
+: InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3),
+mnemonic#"\t$R1, $R2, $R3", []> {
+let M4 = 0;
+}
+class SideEffectTernaryRRFb<string mnemonic, bits<16> opcode,
+RegisterOperand cls1, RegisterOperand cls2,
+RegisterOperand cls3>
+: InstRRFb<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3),
+mnemonic#"\t$R1, $R3, $R2", []> {
+let M4 = 0;
+}
+class SideEffectTernaryMemMemMemRRFb<string mnemonic, bits<16> opcode,
+RegisterOperand cls1,
+RegisterOperand cls2,
+RegisterOperand cls3>
+: InstRRFb<opcode, (outs cls1:$R1, cls2:$R2, cls3:$R3),
+(ins cls1:$R1src, cls2:$R2src, cls3:$R3src),
+mnemonic#"\t$R1, $R3, $R2", []> {
+let Constraints = "$R1 = $R1src, $R2 = $R2src, $R3 = $R3src";
+let DisableEncoding = "$R1src, $R2src, $R3src";
+let M4 = 0;
+}
 class SideEffectTernaryRRFc<string mnemonic, bits<16> opcode,
 RegisterOperand cls1, RegisterOperand cls2,
 Immediate imm>
 : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2, imm:$M3),
+mnemonic#"\t$R1, $R2, $M3", []>;
+multiclass SideEffectTernaryRRFcOpt<string mnemonic, bits<16> opcode,
+RegisterOperand cls1,
+RegisterOperand cls2> {
+def "" : SideEffectTernaryRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
+def Opt : SideEffectBinaryRRFc<mnemonic, opcode, cls1, cls2>;
+}
+class SideEffectTernaryMemMemRRFc<string mnemonic, bits<16> opcode,
+RegisterOperand cls1, RegisterOperand cls2,
+Immediate imm>
+: InstRRFc<opcode, (outs cls1:$R1, cls2:$R2),
+(ins cls1:$R1src, cls2:$R2src, imm:$M3),
 mnemonic#"\t$R1, $R2, $M3", []> {
-let hasSideEffects = 1;
+let Constraints = "$R1 = $R1src, $R2 = $R2src";
+let DisableEncoding = "$R1src, $R2src";
+}
+multiclass SideEffectTernaryMemMemRRFcOpt<string mnemonic, bits<16> opcode,
+RegisterOperand cls1,
+RegisterOperand cls2> {
+def "" : SideEffectTernaryMemMemRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
+def Opt : SideEffectBinaryMemMemRRFc<mnemonic, opcode, cls1, cls2>;
 }
 class SideEffectTernarySSF<string mnemonic, bits<12> opcode,
 RegisterOperand cls>
 : InstSSF<opcode, (outs),
 (ins bdaddr12only:$BD1, bdaddr12only:$BD2, cls:$R3),
-mnemonic#"\t$BD1, $BD2, $R3", []> {
+mnemonic#"\t$BD1, $BD2, $R3", []>;
-let hasSideEffects = 1;
+class TernaryRRFa<string mnemonic, bits<16> opcode,
+RegisterOperand cls1, RegisterOperand cls2,
+RegisterOperand cls3>
+: InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3, imm32zx4:$M4),
+mnemonic#"\t$R1, $R2, $R3, $M4", []>;
+class TernaryRRFb<string mnemonic, bits<16> opcode,
+RegisterOperand cls1, RegisterOperand cls2,
+RegisterOperand cls3>
+: InstRRFb<opcode, (outs cls1:$R1, cls3:$R3),
+(ins cls1:$R1src, cls2:$R2, imm32zx4:$M4),
+mnemonic#"\t$R1, $R3, $R2, $M4", []> {
+let Constraints = "$R1 = $R1src";
+let DisableEncoding = "$R1src";
 }
 class TernaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
 RegisterOperand cls2>
 : InstRRFe<opcode, (outs cls1:$R1),
 (ins imm32zx4:$M3, cls2:$R2, imm32zx4:$M4),
 mnemonic#"\t$R1, $M3, $R2, $M4", []>;
-class TernaryRRD<string mnemonic, bits<16> opcode,
+class TernaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator,
-SDPatternOperator operator, RegisterOperand cls>
+RegisterOperand cls1, RegisterOperand cls2>
-: InstRRD<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, cls:$R2),
+: InstRRD<opcode, (outs cls1:$R1), (ins cls2:$R1src, cls2:$R3, cls2:$R2),
 mnemonic#"\t$R1, $R3, $R2",
-[(set cls:$R1, (operator cls:$R1src, cls:$R3, cls:$R2))]> {
+[(set cls1:$R1, (operator cls2:$R1src, cls2:$R3, cls2:$R2))]> {
 let OpKey = mnemonic#cls;
 let OpType = "reg";
 let Constraints = "$R1 = $R1src";
 let DisableEncoding = "$R1src";
 }
 let DispSize = "20" in
 def Y  : TernaryRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>;
 }
 }
+class SideEffectTernaryRS<string mnemonic, bits<8> opcode,
+RegisterOperand cls1, RegisterOperand cls2>
+: InstRSa<opcode, (outs),
+(ins cls1:$R1, cls2:$R3, bdaddr12only:$BD2),
+mnemonic#"\t$R1, $R3, $BD2", []>;
+class SideEffectTernaryRSY<string mnemonic, bits<16> opcode,
+RegisterOperand cls1, RegisterOperand cls2>
+: InstRSYa<opcode, (outs),
+(ins cls1:$R1, cls2:$R3, bdaddr20only:$BD2),
+mnemonic#"\t$R1, $R3, $BD2", []>;
+class SideEffectTernaryMemMemRS<string mnemonic, bits<8> opcode,
+RegisterOperand cls1, RegisterOperand cls2>
+: InstRSa<opcode, (outs cls1:$R1, cls2:$R3),
+(ins cls1:$R1src, cls2:$R3src, shift12only:$BD2),
+mnemonic#"\t$R1, $R3, $BD2", []> {
+let Constraints = "$R1 = $R1src, $R3 = $R3src";
+let DisableEncoding = "$R1src, $R3src";
+}
+class SideEffectTernaryMemMemRSY<string mnemonic, bits<16> opcode,
+RegisterOperand cls1, RegisterOperand cls2>
+: InstRSYa<opcode, (outs cls1:$R1, cls2:$R3),
+(ins cls1:$R1src, cls2:$R3src, shift20only:$BD2),
+mnemonic#"\t$R1, $R3, $BD2", []> {
+let Constraints = "$R1 = $R1src, $R3 = $R3src";
+let DisableEncoding = "$R1src, $R3src";
+}
 class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
-RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
+RegisterOperand cls1, RegisterOperand cls2,
-: InstRXF<opcode, (outs cls:$R1),
+SDPatternOperator load, bits<5> bytes>
-(ins cls:$R1src, cls:$R3, bdxaddr12only:$XBD2),
+: InstRXF<opcode, (outs cls1:$R1),
+(ins cls2:$R1src, cls2:$R3, bdxaddr12only:$XBD2),
 mnemonic#"\t$R1, $R3, $XBD2",
-[(set cls:$R1, (operator cls:$R1src, cls:$R3,
+[(set cls1:$R1, (operator cls2:$R1src, cls2:$R3,
 (load bdxaddr12only:$XBD2)))]> {
 let OpKey = mnemonic#"r"#cls;
 let OpType = "mem";
 let Constraints = "$R1 = $R1src";
 let DisableEncoding = "$R1src";
 let mayLoad = 1;
 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
 (tr2.vt tr2.op:$V3),
 imm32zx8:$I4)))]> {
 let M5 = type;
 }
+class TernaryVRIi<string mnemonic, bits<16> opcode, RegisterOperand cls>
+: InstVRIi<opcode, (outs VR128:$V1),
+(ins cls:$R2, imm32zx8:$I3, imm32zx4:$M4),
+mnemonic#"\t$V1, $R2, $I3, $M4", []>;
 class TernaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m4or>
 : InstVRRa<opcode, (outs tr1.op:$V1),
 (ins tr2.op:$V2, imm32zx4:$M4, imm32zx4:$M5),
 imm32zx4:$M4)))]> {
 let M5 = 0;
 let M6 = 0;
 }
+class TernaryVRRcFloat<string mnemonic, bits<16> opcode,
+SDPatternOperator operator, TypedReg tr1, TypedReg tr2,
+bits<4> type = 0, bits<4> m5 = 0>
+: InstVRRc<opcode, (outs tr1.op:$V1),
+(ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M6),
+mnemonic#"\t$V1, $V2, $V3, $M6",
+[(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
+(tr2.vt tr2.op:$V3),
+imm32zx4:$M6)))]> {
+let M4 = type;
+let M5 = m5;
+}
+class TernaryVRRcFloatGeneric<string mnemonic, bits<16> opcode>
+: InstVRRc<opcode, (outs VR128:$V1),
+(ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
+imm32zx4:$M6),
+mnemonic#"\t$V1, $V2, $V3, $M4, $M5, $M6", []>;
 class TernaryVRRd<string mnemonic, bits<16> opcode, SDPatternOperator operator,
 TypedReg tr1, TypedReg tr2, bits<4> type = 0>
 : InstVRRd<opcode, (outs tr1.op:$V1),
 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
 mnemonic#"\t$V1, $V2, $V3, $V4",
 mnemonic#"\t$V1, $V2, $V3, $I4, $M5", []> {
 let Constraints = "$V1 = $V1src";
 let DisableEncoding = "$V1src";
 }
+class QuaternaryVRIf<string mnemonic, bits<16> opcode>
+: InstVRIf<opcode, (outs VR128:$V1),
+(ins VR128:$V2, VR128:$V3,
+imm32zx8:$I4, imm32zx4:$M5),
+mnemonic#"\t$V1, $V2, $V3, $I4, $M5", []>;
+class QuaternaryVRIg<string mnemonic, bits<16> opcode>
+: InstVRIg<opcode, (outs VR128:$V1),
+(ins VR128:$V2, imm32zx8:$I3,
+imm32zx8:$I4, imm32zx4:$M5),
+mnemonic#"\t$V1, $V2, $I3, $I4, $M5", []>;
 class QuaternaryVRRd<string mnemonic, bits<16> opcode,
 SDPatternOperator operator, TypedReg tr1, TypedReg tr2,
-bits<4> type, SDPatternOperator m6mask, bits<4> m6or>
+TypedReg tr3, TypedReg tr4, bits<4> type,
+SDPatternOperator m6mask = imm32zx4, bits<4> m6or = 0>
 : InstVRRd<opcode, (outs tr1.op:$V1),
-(ins tr2.op:$V2, tr2.op:$V3, tr2.op:$V4, m6mask:$M6),
+(ins tr2.op:$V2, tr3.op:$V3, tr4.op:$V4, m6mask:$M6),
 mnemonic#"\t$V1, $V2, $V3, $V4, $M6",
 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
-(tr2.vt tr2.op:$V3),
+(tr3.vt tr3.op:$V3),
-(tr2.vt tr2.op:$V4),
+(tr4.vt tr4.op:$V4),
 m6mask:$M6)))],
 m6or> {
 let M5 = type;
 }
+class QuaternaryVRRdGeneric<string mnemonic, bits<16> opcode>
+: InstVRRd<opcode, (outs VR128:$V1),
+(ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
+mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
 // Declare a pair of instructions, one which sets CC and one which doesn't.
 // The CC-setting form ends with "S" and sets the low bit of M6.
 // Also create aliases to make use of M6 operand optional in assembler.
 multiclass QuaternaryOptVRRdSPair<string mnemonic, bits<16> opcode,
 SDPatternOperator operator,
 SDPatternOperator operator_cc,
 TypedReg tr1, TypedReg tr2, bits<4> type,
 bits<4> modifier = 0> {
-def "" : QuaternaryVRRd<mnemonic, opcode, operator, tr1, tr2, type,
+def "" : QuaternaryVRRd<mnemonic, opcode, operator,
+tr1, tr2, tr2, tr2, type,
 imm32zx4even, !and (modifier, 14)>;
 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4",
 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
 tr2.op:$V3, tr2.op:$V4, 0)>;
 let Defs = [CC] in
-def S : QuaternaryVRRd<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
+def S : QuaternaryVRRd<mnemonic##"s", opcode, operator_cc,
+tr1, tr2, tr2, tr2, type,
 imm32zx4even, !add (!and (modifier, 14), 1)>;
 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3, $V4",
 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
 tr2.op:$V3, tr2.op:$V4, 0)>;
 }
 multiclass QuaternaryOptVRRdSPairGeneric<string mnemonic, bits<16> opcode> {
-def "" : InstVRRd<opcode, (outs VR128:$V1),
+def "" : QuaternaryVRRdGeneric<mnemonic, opcode>;
-(ins VR128:$V2, VR128:$V3, VR128:$V4,
-imm32zx4:$M5, imm32zx4:$M6),
-mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4, $M5",
 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
 VR128:$V4, imm32zx4:$M5, 0)>;
 }
+class SideEffectQuaternaryRRFa<string mnemonic, bits<16> opcode,
+RegisterOperand cls1, RegisterOperand cls2,
+RegisterOperand cls3>
+: InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3, imm32zx4:$M4),
+mnemonic#"\t$R1, $R2, $R3, $M4", []>;
+multiclass SideEffectQuaternaryRRFaOptOpt<string mnemonic, bits<16> opcode,
+RegisterOperand cls1,
+RegisterOperand cls2,
+RegisterOperand cls3> {
+def "" : SideEffectQuaternaryRRFa<mnemonic, opcode, cls1, cls2, cls3>;
+def Opt : SideEffectTernaryRRFa<mnemonic, opcode, cls1, cls2, cls3>;
+def OptOpt : SideEffectBinaryRRFa<mnemonic, opcode, cls1, cls2>;
+}
+class SideEffectQuaternaryRRFb<string mnemonic, bits<16> opcode,
+RegisterOperand cls1, RegisterOperand cls2,
+RegisterOperand cls3>
+: InstRRFb<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3, imm32zx4:$M4),
+mnemonic#"\t$R1, $R3, $R2, $M4", []>;
+multiclass SideEffectQuaternaryRRFbOpt<string mnemonic, bits<16> opcode,
+RegisterOperand cls1,
+RegisterOperand cls2,
+RegisterOperand cls3> {
+def "" : SideEffectQuaternaryRRFb<mnemonic, opcode, cls1, cls2, cls3>;
+def Opt : SideEffectTernaryRRFb<mnemonic, opcode, cls1, cls2, cls3>;
+}
+class SideEffectQuaternarySSe<string mnemonic, bits<8> opcode,
+RegisterOperand cls>
+: InstSSe<opcode, (outs),
+(ins cls:$R1, bdaddr12only:$BD2, cls:$R3, bdaddr12only:$BD4),
+mnemonic#"\t$R1, $BD2, $R3, $BD4", []>;
 class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
 RegisterOperand cls, AddressingMode mode = bdaddr20only>
 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
 mnemonic#"\t$R1, $R3, $BD2",
 [(set cls:$R1, (operator mode:$BD2, cls:$R3))]> {
+let mayLoad = 1;
+let mayStore = 1;
+}
+class CmpSwapRRE<string mnemonic, bits<16> opcode,
+RegisterOperand cls1, RegisterOperand cls2>
+: InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
+mnemonic#"\t$R1, $R2", []> {
+let Constraints = "$R1 = $R1src";
+let DisableEncoding = "$R1src";
 let mayLoad = 1;
 let mayStore = 1;
 }
 class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
 // However, BDXs have two extra operands and are therefore 6 units more
 // complex.
 let AddedComplexity = 7;
 }
+class BranchPreloadSMI<string mnemonic, bits<8> opcode>
+: InstSMI<opcode, (outs),
+(ins imm32zx4:$M1, brtarget16bpp:$RI2, bdxaddr12only:$BD3),
+mnemonic#"\t$M1, $RI2, $BD3", []>;
+class BranchPreloadMII<string mnemonic, bits<8> opcode>
+: InstMII<opcode, (outs),
+(ins imm32zx4:$M1, brtarget12bpp:$RI2, brtarget24bpp:$RI3),
+mnemonic#"\t$M1, $RI2, $RI3", []>;
 // A floating-point load-and test operation.  Create both a normal unary
 // operation and one that acts as a comparison against zero.
 // Note that the comparison against zero operation is not available if we
 // have vector support, since load-and-test instructions will partially
 }
 // Like SideEffectBinarySIL, but expanded later.
 class SideEffectBinarySILPseudo<SDPatternOperator operator, Immediate imm>
 : Pseudo<(outs), (ins bdaddr12only:$BD1, imm:$I2),
-[(operator bdaddr12only:$BD1, imm:$I2)]> {
+[(operator bdaddr12only:$BD1, imm:$I2)]>;
-let hasSideEffects = 1;
-}
 // Like UnaryRI, but expanded after RA depending on the choice of register.
 class UnaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
 Immediate imm>
 : Pseudo<(outs cls:$R1), (ins imm:$I2),
 }
 // Like CompareRI, but expanded after RA depending on the choice of register.
 class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls,
 Immediate imm>
-: Pseudo<(outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]>;
+: Pseudo<(outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]> {
+let isCompare = 1;
+}
 // Like CompareRXY, but expanded after RA depending on the choice of register.
 class CompareRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
 SDPatternOperator load, bits<5> bytes,
 AddressingMode mode = bdxaddr20only>
 [(operator cls:$R1, (load mode:$XBD2))]> {
 let mayLoad = 1;
 let Has20BitOffset = 1;
 let HasIndex = 1;
 let AccessBytes = bytes;
+}
+// Like CondBinaryRRF, but expanded after RA depending on the choice of
+// register.
+class CondBinaryRRFPseudo<RegisterOperand cls1, RegisterOperand cls2>
+: Pseudo<(outs cls1:$R1),
+(ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3), []> {
+let Constraints = "$R1 = $R1src";
+let DisableEncoding = "$R1src";
+let CCMaskLast = 1;
+}
+// Like CondBinaryRIE, but expanded after RA depending on the choice of
+// register.
+class CondBinaryRIEPseudo<RegisterOperand cls, Immediate imm>
+: Pseudo<(outs cls:$R1),
+(ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
+[(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src,
+cond4:$valid, cond4:$M3))]> {
+let Constraints = "$R1 = $R1src";
+let DisableEncoding = "$R1src";
+let CCMaskLast = 1;
+}
+// Like CondUnaryRSY, but expanded after RA depending on the choice of
+// register.
+class CondUnaryRSYPseudo<SDPatternOperator operator, RegisterOperand cls,
+bits<5> bytes, AddressingMode mode = bdaddr20only>
+: Pseudo<(outs cls:$R1),
+(ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$R3),
+[(set cls:$R1,
+(z_select_ccmask (operator mode:$BD2), cls:$R1src,
+cond4:$valid, cond4:$R3))]> {
+let Constraints = "$R1 = $R1src";
+let DisableEncoding = "$R1src";
+let mayLoad = 1;
+let AccessBytes = bytes;
+let CCMaskLast = 1;
+}
+// Like CondStoreRSY, but expanded after RA depending on the choice of
+// register.
+class CondStoreRSYPseudo<RegisterOperand cls, bits<5> bytes,
+AddressingMode mode = bdaddr20only>
+: Pseudo<(outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$R3), []> {
+let mayStore = 1;
+let AccessBytes = bytes;
+let CCMaskLast = 1;
 }
 // Like StoreRXY, but expanded after RA depending on the choice of register.
 class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
 bits<5> bytes, AddressingMode mode = bdxaddr20only>
 let DisableEncoding = "$R1src";
 }
 // Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is
 // the value of the PSW's 2-bit condition code field.
-class SelectWrapper<RegisterOperand cls>
+class SelectWrapper<ValueType vt, RegisterOperand cls>
 : Pseudo<(outs cls:$dst),
 (ins cls:$src1, cls:$src2, imm32zx4:$valid, imm32zx4:$cc),
-[(set cls:$dst, (z_select_ccmask cls:$src1, cls:$src2,
+[(set (vt cls:$dst), (z_select_ccmask cls:$src1, cls:$src2,
 imm32zx4:$valid, imm32zx4:$cc))]> {
 let usesCustomInserter = 1;
 // Although the instructions used by these nodes do not in themselves
 // change CC, the insertion requires new blocks, and CC cannot be live
 // across them.
 // The Sequence form uses a straight-line sequence of instructions and
 // the Loop form uses a loop of length-256 instructions followed by
 // another instruction to handle the excess.
 multiclass MemorySS<string mnemonic, bits<8> opcode,
 SDPatternOperator sequence, SDPatternOperator loop> {
-def "" : InstSSa<opcode, (outs), (ins bdladdr12onlylen8:$BDL1,
+def "" : SideEffectBinarySSa<mnemonic, opcode>;
-bdaddr12only:$BD2),
-mnemonic##"\t$BDL1, $BD2", []>;
 let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
 def Sequence : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
 imm64:$length),
 [(sequence bdaddr12only:$dest, bdaddr12only:$src,
 imm64:$length)]>;
 // number of bytes at a time and sets CC to 3 if the instruction needs
 // to be repeated.  Also define a pseudo instruction that represents
 // the full loop (the main instruction plus the branch on CC==3).
 multiclass StringRRE<string mnemonic, bits<16> opcode,
 SDPatternOperator operator> {
-def "" : InstRRE<opcode, (outs GR64:$R1, GR64:$R2),
+let Uses = [R0L] in
-(ins GR64:$R1src, GR64:$R2src),
+def "" : SideEffectBinaryMemMemRRE<mnemonic, opcode, GR64, GR64>;
-mnemonic#"\t$R1, $R2", []> {
-let Uses = [R0L];
-let Constraints = "$R1 = $R1src, $R2 = $R2src";
-let DisableEncoding = "$R1src, $R2src";
-}
 let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in
 def Loop : Pseudo<(outs GR64:$end),
 (ins GR64:$start1, GR64:$start2, GR32:$char),
 [(set GR64:$end, (operator GR64:$start1, GR64:$start2,
 GR32:$char))]>;

Mercurial > hg > CbC > CbC_llvm

comparison lib/Target/SystemZ/SystemZInstrFormats.td @ 121:803732b1fca8