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comparison test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
parents 1172e4bd9c6f
children c2174574ed3a
comparison
equal deleted inserted replaced
120:1172e4bd9c6f 121:803732b1fca8
1 ; RUN: llc -march=amdgcn -mcpu=SI -o - %s | FileCheck %s 1 ; RUN: llc -march=amdgcn -mcpu=tahiti -o - %s | FileCheck %s
2 ; Don't crash when the use of an undefined value is only detected by the 2 ; Don't crash when the use of an undefined value is only detected by the
3 ; register coalescer because it is hidden with subregister insert/extract. 3 ; register coalescer because it is hidden with subregister insert/extract.
4 target triple="amdgcn--" 4 target triple="amdgcn--"
5 5
6 ; CHECK-LABEL: foobar: 6 ; CHECK-LABEL: foobar:
8 ; CHECK-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb 8 ; CHECK-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb
9 ; CHECK-NEXT: s_waitcnt lgkmcnt(0) 9 ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
10 ; CHECK: v_mbcnt_lo_u32_b32_e64 10 ; CHECK: v_mbcnt_lo_u32_b32_e64
11 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 11 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
12 ; CHECK-NEXT: s_and_saveexec_b64 s[2:3], vcc 12 ; CHECK-NEXT: s_and_saveexec_b64 s[2:3], vcc
13 ; CHECK-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
14 ; BB0_1: 13 ; BB0_1:
15 ; CHECK: s_load_dword s0, s[0:1], 0xa 14 ; CHECK: s_load_dword s0, s[0:1], 0xa
16 ; CHECK-NEXT: s_waitcnt lgkmcnt(0) 15 ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
17 ; BB0_2: 16 ; BB0_2:
18 ; CHECK: s_or_b64 exec, exec, s[2:3] 17 ; CHECK: s_or_b64 exec, exec, s[2:3]
19 ; CHECK-NEXT: s_mov_b32 s7, 0xf000 18 ; CHECK-NEXT: s_mov_b32 s7, 0xf000
20 ; CHECK-NEXT: s_mov_b32 s6, -1 19 ; CHECK-NEXT: s_mov_b32 s6, -1
21 ; CHECK-NEXT: buffer_store_dword v1, off, s[4:7], 0 20 ; CHECK-NEXT: buffer_store_dword v1, off, s[4:7], 0
22 ; CHECK-NEXT: s_endpgm 21 ; CHECK-NEXT: s_endpgm
23 define void @foobar(float %a0, float %a1, float addrspace(1)* %out) nounwind { 22 define amdgpu_kernel void @foobar(float %a0, float %a1, float addrspace(1)* %out) nounwind {
24 entry: 23 entry:
25 %v0 = insertelement <4 x float> undef, float %a0, i32 0 24 %v0 = insertelement <4 x float> undef, float %a0, i32 0
26 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 25 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
27 %cnd = icmp eq i32 %tid, 0 26 %cnd = icmp eq i32 %tid, 0
28 br i1 %cnd, label %ift, label %ife 27 br i1 %cnd, label %ift, label %ife