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comparison test/CodeGen/PowerPC/ifcvt.ll @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
parents 95c75e76d11b
children
comparison
equal deleted inserted replaced
120:1172e4bd9c6f 121:803732b1fca8
1 ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s 1 ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s
2 ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs -ppc-gen-isel=false | FileCheck --check-prefix=CHECK-NO-ISEL %s
2 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" 3 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
3 target triple = "powerpc64-unknown-linux-gnu" 4 target triple = "powerpc64-unknown-linux-gnu"
4 5
5 define i32 @test(i32 %a, i32 %b, i32 %c, i32 %d) { 6 define i32 @test(i32 %a, i32 %b, i32 %c, i32 %d) {
6 entry: 7 entry:
16 17
17 cond.false: ; preds = %sw.epilog 18 cond.false: ; preds = %sw.epilog
18 %add37 = add nsw i32 %conv29, %a 19 %add37 = add nsw i32 %conv29, %a
19 br label %cond.end 20 br label %cond.end
20 21
21 ; CHECK: @test 22 ; CHECK-LABEL: @test
23 ; CHECK-NO-ISEL-LABEL: @test
22 ; CHECK: add [[REG:[0-9]+]], 24 ; CHECK: add [[REG:[0-9]+]],
23 ; CHECK: subf [[REG2:[0-9]+]], 25 ; CHECK: subf [[REG2:[0-9]+]],
24 ; CHECK: isel {{[0-9]+}}, [[REG]], [[REG2]], 26 ; CHECK: isel {{[0-9]+}}, [[REG]], [[REG2]],
27 ; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
28 ; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
29 ; CHECK-NO-ISEL: [[TRUE]]
30 ; CHECK-NO-ISEL-NEXT: addi 5, 6, 0
31 ; CHECK-NO-ISEL: extsh 5, 5
32 ; CHECK-NO-ISEL-NEXT: add 3, 3, 5
33 ; CHECK-NO-ISEL-NEXT: blr
25 34
26 cond.end: ; preds = %cond.false, %cond.true 35 cond.end: ; preds = %cond.false, %cond.true
27 %cond = phi i32 [ %sub34, %cond.true ], [ %add37, %cond.false ] 36 %cond = phi i32 [ %sub34, %cond.true ], [ %add37, %cond.false ]
28 %sext83 = shl i32 %cond, 16 37 %sext83 = shl i32 %cond, 16
29 %conv39 = ashr exact i32 %sext83, 16 38 %conv39 = ashr exact i32 %sext83, 16