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comparison test/CodeGen/X86/rot16.ll @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
parents e4204d083e25
children 3a76565eade5
comparison
equal deleted inserted replaced
120:1172e4bd9c6f 121:803732b1fca8
1 ; RUN: llc < %s -march=x86 -mcpu=generic | FileCheck %s 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X32
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64
2 4
3 define i16 @foo(i16 %x, i16 %y, i16 %z) nounwind readnone { 5 define i16 @foo(i16 %x, i16 %y, i16 %z) nounwind {
4 entry: 6 ; X32-LABEL: foo:
5 ; CHECK-LABEL: foo: 7 ; X32: # BB#0:
6 ; CHECK: rolw %cl 8 ; X32-NEXT: movb {{[0-9]+}}(%esp), %cl
7 %0 = shl i16 %x, %z 9 ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
8 %1 = sub i16 16, %z 10 ; X32-NEXT: rolw %cl, %ax
9 %2 = lshr i16 %x, %1 11 ; X32-NEXT: retl
10 %3 = or i16 %2, %0 12 ;
11 ret i16 %3 13 ; X64-LABEL: foo:
14 ; X64: # BB#0:
15 ; X64-NEXT: movl %edx, %ecx
16 ; X64-NEXT: shldw %cl, %di, %di
17 ; X64-NEXT: movl %edi, %eax
18 ; X64-NEXT: retq
19 %t0 = shl i16 %x, %z
20 %t1 = sub i16 16, %z
21 %t2 = lshr i16 %x, %t1
22 %t3 = or i16 %t2, %t0
23 ret i16 %t3
12 } 24 }
13 25
14 define i16 @bar(i16 %x, i16 %y, i16 %z) nounwind readnone { 26 define i16 @bar(i16 %x, i16 %y, i16 %z) nounwind {
15 entry: 27 ; X32-LABEL: bar:
16 ; CHECK-LABEL: bar: 28 ; X32: # BB#0:
17 ; CHECK: shldw %cl 29 ; X32-NEXT: movb {{[0-9]+}}(%esp), %cl
18 %0 = shl i16 %y, %z 30 ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %edx
19 %1 = sub i16 16, %z 31 ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
20 %2 = lshr i16 %x, %1 32 ; X32-NEXT: shldw %cl, %dx, %ax
21 %3 = or i16 %2, %0 33 ; X32-NEXT: retl
22 ret i16 %3 34 ;
35 ; X64-LABEL: bar:
36 ; X64: # BB#0:
37 ; X64-NEXT: movl %edx, %ecx
38 ; X64-NEXT: shldw %cl, %di, %si
39 ; X64-NEXT: movl %esi, %eax
40 ; X64-NEXT: retq
41 %t0 = shl i16 %y, %z
42 %t1 = sub i16 16, %z
43 %t2 = lshr i16 %x, %t1
44 %t3 = or i16 %t2, %t0
45 ret i16 %t3
23 } 46 }
24 47
25 define i16 @un(i16 %x, i16 %y, i16 %z) nounwind readnone { 48 define i16 @un(i16 %x, i16 %y, i16 %z) nounwind {
26 entry: 49 ; X32-LABEL: un:
27 ; CHECK-LABEL: un: 50 ; X32: # BB#0:
28 ; CHECK: rorw %cl 51 ; X32-NEXT: movb {{[0-9]+}}(%esp), %cl
29 %0 = lshr i16 %x, %z 52 ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
30 %1 = sub i16 16, %z 53 ; X32-NEXT: rorw %cl, %ax
31 %2 = shl i16 %x, %1 54 ; X32-NEXT: retl
32 %3 = or i16 %2, %0 55 ;
33 ret i16 %3 56 ; X64-LABEL: un:
57 ; X64: # BB#0:
58 ; X64-NEXT: movl %edx, %ecx
59 ; X64-NEXT: shrdw %cl, %di, %di
60 ; X64-NEXT: movl %edi, %eax
61 ; X64-NEXT: retq
62 %t0 = lshr i16 %x, %z
63 %t1 = sub i16 16, %z
64 %t2 = shl i16 %x, %t1
65 %t3 = or i16 %t2, %t0
66 ret i16 %t3
34 } 67 }
35 68
36 define i16 @bu(i16 %x, i16 %y, i16 %z) nounwind readnone { 69 define i16 @bu(i16 %x, i16 %y, i16 %z) nounwind {
37 entry: 70 ; X32-LABEL: bu:
38 ; CHECK-LABEL: bu: 71 ; X32: # BB#0:
39 ; CHECK: shrdw 72 ; X32-NEXT: movb {{[0-9]+}}(%esp), %cl
40 %0 = lshr i16 %y, %z 73 ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %edx
41 %1 = sub i16 16, %z 74 ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
42 %2 = shl i16 %x, %1 75 ; X32-NEXT: shrdw %cl, %dx, %ax
43 %3 = or i16 %2, %0 76 ; X32-NEXT: retl
44 ret i16 %3 77 ;
78 ; X64-LABEL: bu:
79 ; X64: # BB#0:
80 ; X64-NEXT: movl %edx, %ecx
81 ; X64-NEXT: shrdw %cl, %di, %si
82 ; X64-NEXT: movl %esi, %eax
83 ; X64-NEXT: retq
84 %t0 = lshr i16 %y, %z
85 %t1 = sub i16 16, %z
86 %t2 = shl i16 %x, %t1
87 %t3 = or i16 %t2, %t0
88 ret i16 %t3
45 } 89 }
46 90
47 define i16 @xfoo(i16 %x, i16 %y, i16 %z) nounwind readnone { 91 define i16 @xfoo(i16 %x, i16 %y, i16 %z) nounwind {
48 entry: 92 ; X32-LABEL: xfoo:
49 ; CHECK-LABEL: xfoo: 93 ; X32: # BB#0:
50 ; CHECK: rolw $5 94 ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
51 %0 = lshr i16 %x, 11 95 ; X32-NEXT: rolw $5, %ax
52 %1 = shl i16 %x, 5 96 ; X32-NEXT: retl
53 %2 = or i16 %0, %1 97 ;
54 ret i16 %2 98 ; X64-LABEL: xfoo:
99 ; X64: # BB#0:
100 ; X64-NEXT: rolw $5, %di
101 ; X64-NEXT: movl %edi, %eax
102 ; X64-NEXT: retq
103 %t0 = lshr i16 %x, 11
104 %t1 = shl i16 %x, 5
105 %t2 = or i16 %t0, %t1
106 ret i16 %t2
55 } 107 }
56 108
57 define i16 @xbar(i16 %x, i16 %y, i16 %z) nounwind readnone { 109 define i16 @xbar(i16 %x, i16 %y, i16 %z) nounwind {
58 entry: 110 ; X32-LABEL: xbar:
59 ; CHECK-LABEL: xbar: 111 ; X32: # BB#0:
60 ; CHECK: shldw $5 112 ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
61 %0 = shl i16 %y, 5 113 ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
62 %1 = lshr i16 %x, 11 114 ; X32-NEXT: shldw $5, %cx, %ax
63 %2 = or i16 %0, %1 115 ; X32-NEXT: retl
64 ret i16 %2 116 ;
117 ; X64-LABEL: xbar:
118 ; X64: # BB#0:
119 ; X64-NEXT: shldw $5, %di, %si
120 ; X64-NEXT: movl %esi, %eax
121 ; X64-NEXT: retq
122 %t0 = shl i16 %y, 5
123 %t1 = lshr i16 %x, 11
124 %t2 = or i16 %t0, %t1
125 ret i16 %t2
65 } 126 }
66 127
67 define i16 @xun(i16 %x, i16 %y, i16 %z) nounwind readnone { 128 define i16 @xun(i16 %x, i16 %y, i16 %z) nounwind {
68 entry: 129 ; X32-LABEL: xun:
69 ; CHECK-LABEL: xun: 130 ; X32: # BB#0:
70 ; CHECK: rolw $11 131 ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
71 %0 = lshr i16 %x, 5 132 ; X32-NEXT: rolw $11, %ax
72 %1 = shl i16 %x, 11 133 ; X32-NEXT: retl
73 %2 = or i16 %0, %1 134 ;
74 ret i16 %2 135 ; X64-LABEL: xun:
136 ; X64: # BB#0:
137 ; X64-NEXT: rolw $11, %di
138 ; X64-NEXT: movl %edi, %eax
139 ; X64-NEXT: retq
140 %t0 = lshr i16 %x, 5
141 %t1 = shl i16 %x, 11
142 %t2 = or i16 %t0, %t1
143 ret i16 %t2
75 } 144 }
76 145
77 define i16 @xbu(i16 %x, i16 %y, i16 %z) nounwind readnone { 146 define i16 @xbu(i16 %x, i16 %y, i16 %z) nounwind {
78 entry: 147 ; X32-LABEL: xbu:
79 ; CHECK-LABEL: xbu: 148 ; X32: # BB#0:
80 ; CHECK: shldw $11 149 ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
81 %0 = lshr i16 %y, 5 150 ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
82 %1 = shl i16 %x, 11 151 ; X32-NEXT: shldw $11, %cx, %ax
83 %2 = or i16 %0, %1 152 ; X32-NEXT: retl
84 ret i16 %2 153 ;
154 ; X64-LABEL: xbu:
155 ; X64: # BB#0:
156 ; X64-NEXT: shldw $11, %si, %di
157 ; X64-NEXT: movl %edi, %eax
158 ; X64-NEXT: retq
159 %t0 = lshr i16 %y, 5
160 %t1 = shl i16 %x, 11
161 %t2 = or i16 %t0, %t1
162 ret i16 %t2
85 } 163 }