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comparison test/CodeGen/X86/vec_sdiv_to_shift.ll @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
parents 1172e4bd9c6f
children 3a76565eade5
comparison
equal deleted inserted replaced
120:1172e4bd9c6f 121:803732b1fca8
45 ; AVX-NEXT: vpsraw $5, %xmm0, %xmm0 45 ; AVX-NEXT: vpsraw $5, %xmm0, %xmm0
46 ; AVX-NEXT: retq 46 ; AVX-NEXT: retq
47 entry: 47 entry:
48 %0 = sdiv <8 x i16> %var, <i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32> 48 %0 = sdiv <8 x i16> %var, <i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32>
49 ret <8 x i16> %0 49 ret <8 x i16> %0
50 }
51
52 define <4 x i32> @sdiv_zero(<4 x i32> %var) {
53 ; SSE-LABEL: sdiv_zero:
54 ; SSE: # BB#0: # %entry
55 ; SSE-NEXT: pextrd $1, %xmm0, %eax
56 ; SSE-NEXT: xorl %esi, %esi
57 ; SSE-NEXT: cltd
58 ; SSE-NEXT: idivl %esi
59 ; SSE-NEXT: movl %eax, %ecx
60 ; SSE-NEXT: movd %xmm0, %eax
61 ; SSE-NEXT: cltd
62 ; SSE-NEXT: idivl %esi
63 ; SSE-NEXT: movd %eax, %xmm1
64 ; SSE-NEXT: pinsrd $1, %ecx, %xmm1
65 ; SSE-NEXT: pextrd $2, %xmm0, %eax
66 ; SSE-NEXT: cltd
67 ; SSE-NEXT: idivl %esi
68 ; SSE-NEXT: pinsrd $2, %eax, %xmm1
69 ; SSE-NEXT: pextrd $3, %xmm0, %eax
70 ; SSE-NEXT: cltd
71 ; SSE-NEXT: idivl %esi
72 ; SSE-NEXT: pinsrd $3, %eax, %xmm1
73 ; SSE-NEXT: movdqa %xmm1, %xmm0
74 ; SSE-NEXT: retq
75 ;
76 ; AVX-LABEL: sdiv_zero:
77 ; AVX: # BB#0: # %entry
78 ; AVX-NEXT: vpextrd $1, %xmm0, %eax
79 ; AVX-NEXT: xorl %esi, %esi
80 ; AVX-NEXT: cltd
81 ; AVX-NEXT: idivl %esi
82 ; AVX-NEXT: movl %eax, %ecx
83 ; AVX-NEXT: vmovd %xmm0, %eax
84 ; AVX-NEXT: cltd
85 ; AVX-NEXT: idivl %esi
86 ; AVX-NEXT: vmovd %eax, %xmm1
87 ; AVX-NEXT: vpinsrd $1, %ecx, %xmm1, %xmm1
88 ; AVX-NEXT: vpextrd $2, %xmm0, %eax
89 ; AVX-NEXT: cltd
90 ; AVX-NEXT: idivl %esi
91 ; AVX-NEXT: vpinsrd $2, %eax, %xmm1, %xmm1
92 ; AVX-NEXT: vpextrd $3, %xmm0, %eax
93 ; AVX-NEXT: cltd
94 ; AVX-NEXT: idivl %esi
95 ; AVX-NEXT: vpinsrd $3, %eax, %xmm1, %xmm0
96 ; AVX-NEXT: retq
97 entry:
98 %0 = sdiv <4 x i32> %var, <i32 0, i32 0, i32 0, i32 0>
99 ret <4 x i32> %0
100 } 50 }
101 51
102 define <4 x i32> @sdiv_vec4x32(<4 x i32> %var) { 52 define <4 x i32> @sdiv_vec4x32(<4 x i32> %var) {
103 ; SSE-LABEL: sdiv_vec4x32: 53 ; SSE-LABEL: sdiv_vec4x32:
104 ; SSE: # BB#0: # %entry 54 ; SSE: # BB#0: # %entry
232 entry: 182 entry:
233 %a0 = sdiv <16 x i16> %var, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4> 183 %a0 = sdiv <16 x i16> %var, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
234 ret <16 x i16> %a0 184 ret <16 x i16> %a0
235 } 185 }
236 186
187 ; Div-by-0 in any lane is UB.
188
237 define <4 x i32> @sdiv_non_splat(<4 x i32> %x) { 189 define <4 x i32> @sdiv_non_splat(<4 x i32> %x) {
238 ; SSE-LABEL: sdiv_non_splat: 190 ; SSE-LABEL: sdiv_non_splat:
239 ; SSE: # BB#0: 191 ; SSE: # BB#0:
240 ; SSE-NEXT: pextrd $1, %xmm0, %eax
241 ; SSE-NEXT: xorl %ecx, %ecx
242 ; SSE-NEXT: cltd
243 ; SSE-NEXT: idivl %ecx
244 ; SSE-NEXT: movd %xmm0, %edx
245 ; SSE-NEXT: movl %edx, %esi
246 ; SSE-NEXT: shrl $31, %esi
247 ; SSE-NEXT: addl %edx, %esi
248 ; SSE-NEXT: sarl %esi
249 ; SSE-NEXT: movd %esi, %xmm1
250 ; SSE-NEXT: pinsrd $1, %eax, %xmm1
251 ; SSE-NEXT: pextrd $2, %xmm0, %eax
252 ; SSE-NEXT: cltd
253 ; SSE-NEXT: idivl %ecx
254 ; SSE-NEXT: pinsrd $2, %eax, %xmm1
255 ; SSE-NEXT: pextrd $3, %xmm0, %eax
256 ; SSE-NEXT: cltd
257 ; SSE-NEXT: idivl %ecx
258 ; SSE-NEXT: pinsrd $3, %eax, %xmm1
259 ; SSE-NEXT: movdqa %xmm1, %xmm0
260 ; SSE-NEXT: retq 192 ; SSE-NEXT: retq
261 ; 193 ;
262 ; AVX-LABEL: sdiv_non_splat: 194 ; AVX-LABEL: sdiv_non_splat:
263 ; AVX: # BB#0: 195 ; AVX: # BB#0:
264 ; AVX-NEXT: vpextrd $1, %xmm0, %eax
265 ; AVX-NEXT: xorl %ecx, %ecx
266 ; AVX-NEXT: cltd
267 ; AVX-NEXT: idivl %ecx
268 ; AVX-NEXT: vmovd %xmm0, %edx
269 ; AVX-NEXT: movl %edx, %esi
270 ; AVX-NEXT: shrl $31, %esi
271 ; AVX-NEXT: addl %edx, %esi
272 ; AVX-NEXT: sarl %esi
273 ; AVX-NEXT: vmovd %esi, %xmm1
274 ; AVX-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1
275 ; AVX-NEXT: vpextrd $2, %xmm0, %eax
276 ; AVX-NEXT: cltd
277 ; AVX-NEXT: idivl %ecx
278 ; AVX-NEXT: vpinsrd $2, %eax, %xmm1, %xmm1
279 ; AVX-NEXT: vpextrd $3, %xmm0, %eax
280 ; AVX-NEXT: cltd
281 ; AVX-NEXT: idivl %ecx
282 ; AVX-NEXT: vpinsrd $3, %eax, %xmm1, %xmm0
283 ; AVX-NEXT: retq 196 ; AVX-NEXT: retq
284 %y = sdiv <4 x i32> %x, <i32 2, i32 0, i32 0, i32 0> 197 %y = sdiv <4 x i32> %x, <i32 2, i32 0, i32 0, i32 0>
285 ret <4 x i32> %y 198 ret <4 x i32> %y
286 } 199 }