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comparison test/Transforms/LoopVectorize/if-pred-stores.ll @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
parents 1172e4bd9c6f
children c2174574ed3a
comparison
equal deleted inserted replaced
120:1172e4bd9c6f 121:803732b1fca8
1 ; RUN: opt -S -vectorize-num-stores-pred=1 -force-vector-width=1 -force-vector-interleave=2 -loop-vectorize -verify-loop-info -simplifycfg < %s | FileCheck %s --check-prefix=UNROLL 1 ; RUN: opt -S -vectorize-num-stores-pred=1 -force-vector-width=1 -force-vector-interleave=2 -loop-vectorize -verify-loop-info -simplifycfg < %s | FileCheck %s --check-prefix=UNROLL
2 ; RUN: opt -S -vectorize-num-stores-pred=1 -force-vector-width=1 -force-vector-interleave=2 -loop-vectorize -verify-loop-info < %s | FileCheck %s --check-prefix=UNROLL-NOSIMPLIFY 2 ; RUN: opt -S -vectorize-num-stores-pred=1 -force-vector-width=1 -force-vector-interleave=2 -loop-vectorize -verify-loop-info < %s | FileCheck %s --check-prefix=UNROLL-NOSIMPLIFY
3 ; RUN: opt -S -vectorize-num-stores-pred=1 -force-vector-width=2 -force-vector-interleave=1 -loop-vectorize -enable-cond-stores-vec -verify-loop-info -simplifycfg < %s | FileCheck %s --check-prefix=VEC 3 ; RUN: opt -S -vectorize-num-stores-pred=1 -force-vector-width=2 -force-vector-interleave=1 -loop-vectorize -verify-loop-info -simplifycfg < %s | FileCheck %s --check-prefix=VEC
4 4
5 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" 5 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
6 6
7 ; Test predication of stores. 7 ; Test predication of stores.
8 define i32 @test(i32* nocapture %f) #0 { 8 define i32 @test(i32* nocapture %f) #0 {
9 entry: 9 entry:
10 br label %for.body 10 br label %for.body
11 11
12 ; VEC-LABEL: test 12 ; VEC-LABEL: test
13 ; VEC: %[[v0:.+]] = add i64 %index, 0 13 ; VEC: %[[v0:.+]] = add i64 %index, 0
14 ; VEC: %[[v2:.+]] = getelementptr inbounds i32, i32* %f, i64 %[[v0]]
14 ; VEC: %[[v8:.+]] = icmp sgt <2 x i32> %{{.*}}, <i32 100, i32 100> 15 ; VEC: %[[v8:.+]] = icmp sgt <2 x i32> %{{.*}}, <i32 100, i32 100>
15 ; VEC: %[[v9:.+]] = add nsw <2 x i32> %{{.*}}, <i32 20, i32 20> 16 ; VEC: %[[v11:.+]] = extractelement <2 x i1> %[[v8]], i32 0
16 ; VEC: %[[v10:.+]] = and <2 x i1> %[[v8]], <i1 true, i1 true> 17 ; VEC: br i1 %[[v11]], label %[[cond:.+]], label %[[else:.+]]
17 ; VEC: %[[o1:.+]] = or <2 x i1> zeroinitializer, %[[v10]]
18 ; VEC: %[[v11:.+]] = extractelement <2 x i1> %[[o1]], i32 0
19 ; VEC: %[[v12:.+]] = icmp eq i1 %[[v11]], true
20 ; VEC: br i1 %[[v12]], label %[[cond:.+]], label %[[else:.+]]
21 ; 18 ;
22 ; VEC: [[cond]]: 19 ; VEC: [[cond]]:
23 ; VEC: %[[v13:.+]] = extractelement <2 x i32> %[[v9]], i32 0 20 ; VEC: %[[v13:.+]] = extractelement <2 x i32> %wide.load, i32 0
24 ; VEC: %[[v2:.+]] = getelementptr inbounds i32, i32* %f, i64 %[[v0]] 21 ; VEC: %[[v9a:.+]] = add nsw i32 %[[v13]], 20
25 ; VEC: store i32 %[[v13]], i32* %[[v2]], align 4 22 ; VEC: store i32 %[[v9a]], i32* %[[v2]], align 4
26 ; VEC: br label %[[else:.+]] 23 ; VEC: br label %[[else:.+]]
27 ; 24 ;
28 ; VEC: [[else]]: 25 ; VEC: [[else]]:
29 ; VEC: %[[v15:.+]] = extractelement <2 x i1> %[[o1]], i32 1 26 ; VEC: %[[v15:.+]] = extractelement <2 x i1> %[[v8]], i32 1
30 ; VEC: %[[v16:.+]] = icmp eq i1 %[[v15]], true 27 ; VEC: br i1 %[[v15]], label %[[cond2:.+]], label %[[else2:.+]]
31 ; VEC: br i1 %[[v16]], label %[[cond2:.+]], label %[[else2:.+]]
32 ; 28 ;
33 ; VEC: [[cond2]]: 29 ; VEC: [[cond2]]:
34 ; VEC: %[[v17:.+]] = extractelement <2 x i32> %[[v9]], i32 1 30 ; VEC: %[[v17:.+]] = extractelement <2 x i32> %wide.load, i32 1
31 ; VEC: %[[v9b:.+]] = add nsw i32 %[[v17]], 20
35 ; VEC: %[[v1:.+]] = add i64 %index, 1 32 ; VEC: %[[v1:.+]] = add i64 %index, 1
36 ; VEC: %[[v4:.+]] = getelementptr inbounds i32, i32* %f, i64 %[[v1]] 33 ; VEC: %[[v4:.+]] = getelementptr inbounds i32, i32* %f, i64 %[[v1]]
37 ; VEC: store i32 %[[v17]], i32* %[[v4]], align 4 34 ; VEC: store i32 %[[v9b]], i32* %[[v4]], align 4
38 ; VEC: br label %[[else2:.+]] 35 ; VEC: br label %[[else2:.+]]
39 ; 36 ;
40 ; VEC: [[else2]]: 37 ; VEC: [[else2]]:
41 38
42 ; UNROLL-LABEL: test 39 ; UNROLL-LABEL: test
47 ; UNROLL: %[[v1:[a-zA-Z0-9]+]] = getelementptr inbounds i32, i32* %f, i64 %[[IND1]] 44 ; UNROLL: %[[v1:[a-zA-Z0-9]+]] = getelementptr inbounds i32, i32* %f, i64 %[[IND1]]
48 ; UNROLL: %[[v2:[a-zA-Z0-9]+]] = load i32, i32* %[[v0]], align 4 45 ; UNROLL: %[[v2:[a-zA-Z0-9]+]] = load i32, i32* %[[v0]], align 4
49 ; UNROLL: %[[v3:[a-zA-Z0-9]+]] = load i32, i32* %[[v1]], align 4 46 ; UNROLL: %[[v3:[a-zA-Z0-9]+]] = load i32, i32* %[[v1]], align 4
50 ; UNROLL: %[[v4:[a-zA-Z0-9]+]] = icmp sgt i32 %[[v2]], 100 47 ; UNROLL: %[[v4:[a-zA-Z0-9]+]] = icmp sgt i32 %[[v2]], 100
51 ; UNROLL: %[[v5:[a-zA-Z0-9]+]] = icmp sgt i32 %[[v3]], 100 48 ; UNROLL: %[[v5:[a-zA-Z0-9]+]] = icmp sgt i32 %[[v3]], 100
52 ; UNROLL: %[[o1:[a-zA-Z0-9]+]] = or i1 false, %[[v4]] 49 ; UNROLL: br i1 %[[v4]], label %[[cond:[a-zA-Z0-9.]+]], label %[[else:[a-zA-Z0-9.]+]]
53 ; UNROLL: %[[o2:[a-zA-Z0-9]+]] = or i1 false, %[[v5]]
54 ; UNROLL: %[[v8:[a-zA-Z0-9]+]] = icmp eq i1 %[[o1]], true
55 ; UNROLL: br i1 %[[v8]], label %[[cond:[a-zA-Z0-9.]+]], label %[[else:[a-zA-Z0-9.]+]]
56 ; 50 ;
57 ; UNROLL: [[cond]]: 51 ; UNROLL: [[cond]]:
58 ; UNROLL: %[[v6:[a-zA-Z0-9]+]] = add nsw i32 %[[v2]], 20 52 ; UNROLL: %[[v6:[a-zA-Z0-9]+]] = add nsw i32 %[[v2]], 20
59 ; UNROLL: store i32 %[[v6]], i32* %[[v0]], align 4 53 ; UNROLL: store i32 %[[v6]], i32* %[[v0]], align 4
60 ; UNROLL: br label %[[else]] 54 ; UNROLL: br label %[[else]]
61 ; 55 ;
62 ; UNROLL: [[else]]: 56 ; UNROLL: [[else]]:
63 ; UNROLL: %[[v9:[a-zA-Z0-9]+]] = icmp eq i1 %[[o2]], true 57 ; UNROLL: br i1 %[[v5]], label %[[cond2:[a-zA-Z0-9.]+]], label %[[else2:[a-zA-Z0-9.]+]]
64 ; UNROLL: br i1 %[[v9]], label %[[cond2:[a-zA-Z0-9.]+]], label %[[else2:[a-zA-Z0-9.]+]]
65 ; 58 ;
66 ; UNROLL: [[cond2]]: 59 ; UNROLL: [[cond2]]:
67 ; UNROLL: %[[v7:[a-zA-Z0-9]+]] = add nsw i32 %[[v3]], 20 60 ; UNROLL: %[[v7:[a-zA-Z0-9]+]] = add nsw i32 %[[v3]], 20
68 ; UNROLL: store i32 %[[v7]], i32* %[[v1]], align 4 61 ; UNROLL: store i32 %[[v7]], i32* %[[v1]], align 4
69 ; UNROLL: br label %[[else2]] 62 ; UNROLL: br label %[[else2]]
128 121
129 for.inc26: 122 for.inc26:
130 %iNewChunks.1.lcssa = phi i32 [ undef, %for.body9 ], [ %iNewChunks.2, %for.inc23 ] 123 %iNewChunks.1.lcssa = phi i32 [ undef, %for.body9 ], [ %iNewChunks.2, %for.inc23 ]
131 unreachable 124 unreachable
132 } 125 }
126
127 ; VEC-LABEL: @minimal_bit_widths(
128 ;
129 ; In the test below, it's more profitable for the expression feeding the
130 ; conditional store to remain scalar. Since we can only type-shrink vector
131 ; types, we shouldn't try to represent the expression in a smaller type.
132 ;
133 ; VEC: vector.body:
134 ; VEC: %wide.load = load <2 x i8>, <2 x i8>* {{.*}}, align 1
135 ; VEC: br i1 {{.*}}, label %[[IF0:.+]], label %[[CONT0:.+]]
136 ; VEC: [[IF0]]:
137 ; VEC: %[[E0:.+]] = extractelement <2 x i8> %wide.load, i32 0
138 ; VEC: %[[Z0:.+]] = zext i8 %[[E0]] to i32
139 ; VEC: %[[T0:.+]] = trunc i32 %[[Z0]] to i8
140 ; VEC: store i8 %[[T0]], i8* {{.*}}, align 1
141 ; VEC: br label %[[CONT0]]
142 ; VEC: [[CONT0]]:
143 ; VEC: br i1 {{.*}}, label %[[IF1:.+]], label %[[CONT1:.+]]
144 ; VEC: [[IF1]]:
145 ; VEC: %[[E1:.+]] = extractelement <2 x i8> %wide.load, i32 1
146 ; VEC: %[[Z1:.+]] = zext i8 %[[E1]] to i32
147 ; VEC: %[[T1:.+]] = trunc i32 %[[Z1]] to i8
148 ; VEC: store i8 %[[T1]], i8* {{.*}}, align 1
149 ; VEC: br label %[[CONT1]]
150 ; VEC: [[CONT1]]:
151 ; VEC: br i1 {{.*}}, label %middle.block, label %vector.body
152 ;
153 define void @minimal_bit_widths(i1 %c) {
154 entry:
155 br label %for.body
156
157 for.body:
158 %tmp0 = phi i64 [ %tmp6, %for.inc ], [ 0, %entry ]
159 %tmp1 = phi i64 [ %tmp7, %for.inc ], [ undef, %entry ]
160 %tmp2 = getelementptr i8, i8* undef, i64 %tmp0
161 %tmp3 = load i8, i8* %tmp2, align 1
162 br i1 %c, label %if.then, label %for.inc
163
164 if.then:
165 %tmp4 = zext i8 %tmp3 to i32
166 %tmp5 = trunc i32 %tmp4 to i8
167 store i8 %tmp5, i8* %tmp2, align 1
168 br label %for.inc
169
170 for.inc:
171 %tmp6 = add nuw nsw i64 %tmp0, 1
172 %tmp7 = add i64 %tmp1, -1
173 %tmp8 = icmp eq i64 %tmp7, 0
174 br i1 %tmp8, label %for.end, label %for.body
175
176 for.end:
177 ret void
178 }