Mercurial > hg > CbC > CbC_llvm
comparison include/llvm/CodeGen/VirtRegMap.h @ 0:95c75e76d11b LLVM3.4
LLVM 3.4
author | Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> |
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date | Thu, 12 Dec 2013 13:56:28 +0900 |
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children | 54457678186b |
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1 //===-- llvm/CodeGen/VirtRegMap.h - Virtual Register Map -*- C++ -*--------===// | |
2 // | |
3 // The LLVM Compiler Infrastructure | |
4 // | |
5 // This file is distributed under the University of Illinois Open Source | |
6 // License. See LICENSE.TXT for details. | |
7 // | |
8 //===----------------------------------------------------------------------===// | |
9 // | |
10 // This file implements a virtual register map. This maps virtual registers to | |
11 // physical registers and virtual registers to stack slots. It is created and | |
12 // updated by a register allocator and then used by a machine code rewriter that | |
13 // adds spill code and rewrites virtual into physical register references. | |
14 // | |
15 //===----------------------------------------------------------------------===// | |
16 | |
17 #ifndef LLVM_CODEGEN_VIRTREGMAP_H | |
18 #define LLVM_CODEGEN_VIRTREGMAP_H | |
19 | |
20 #include "llvm/ADT/IndexedMap.h" | |
21 #include "llvm/CodeGen/MachineFunctionPass.h" | |
22 #include "llvm/Target/TargetRegisterInfo.h" | |
23 | |
24 namespace llvm { | |
25 class MachineInstr; | |
26 class MachineFunction; | |
27 class MachineRegisterInfo; | |
28 class TargetInstrInfo; | |
29 class raw_ostream; | |
30 class SlotIndexes; | |
31 | |
32 class VirtRegMap : public MachineFunctionPass { | |
33 public: | |
34 enum { | |
35 NO_PHYS_REG = 0, | |
36 NO_STACK_SLOT = (1L << 30)-1, | |
37 MAX_STACK_SLOT = (1L << 18)-1 | |
38 }; | |
39 | |
40 private: | |
41 MachineRegisterInfo *MRI; | |
42 const TargetInstrInfo *TII; | |
43 const TargetRegisterInfo *TRI; | |
44 MachineFunction *MF; | |
45 | |
46 /// Virt2PhysMap - This is a virtual to physical register | |
47 /// mapping. Each virtual register is required to have an entry in | |
48 /// it; even spilled virtual registers (the register mapped to a | |
49 /// spilled register is the temporary used to load it from the | |
50 /// stack). | |
51 IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2PhysMap; | |
52 | |
53 /// Virt2StackSlotMap - This is virtual register to stack slot | |
54 /// mapping. Each spilled virtual register has an entry in it | |
55 /// which corresponds to the stack slot this register is spilled | |
56 /// at. | |
57 IndexedMap<int, VirtReg2IndexFunctor> Virt2StackSlotMap; | |
58 | |
59 /// Virt2SplitMap - This is virtual register to splitted virtual register | |
60 /// mapping. | |
61 IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2SplitMap; | |
62 | |
63 /// createSpillSlot - Allocate a spill slot for RC from MFI. | |
64 unsigned createSpillSlot(const TargetRegisterClass *RC); | |
65 | |
66 VirtRegMap(const VirtRegMap&) LLVM_DELETED_FUNCTION; | |
67 void operator=(const VirtRegMap&) LLVM_DELETED_FUNCTION; | |
68 | |
69 public: | |
70 static char ID; | |
71 VirtRegMap() : MachineFunctionPass(ID), Virt2PhysMap(NO_PHYS_REG), | |
72 Virt2StackSlotMap(NO_STACK_SLOT), Virt2SplitMap(0) { } | |
73 virtual bool runOnMachineFunction(MachineFunction &MF); | |
74 | |
75 virtual void getAnalysisUsage(AnalysisUsage &AU) const { | |
76 AU.setPreservesAll(); | |
77 MachineFunctionPass::getAnalysisUsage(AU); | |
78 } | |
79 | |
80 MachineFunction &getMachineFunction() const { | |
81 assert(MF && "getMachineFunction called before runOnMachineFunction"); | |
82 return *MF; | |
83 } | |
84 | |
85 MachineRegisterInfo &getRegInfo() const { return *MRI; } | |
86 const TargetRegisterInfo &getTargetRegInfo() const { return *TRI; } | |
87 | |
88 void grow(); | |
89 | |
90 /// @brief returns true if the specified virtual register is | |
91 /// mapped to a physical register | |
92 bool hasPhys(unsigned virtReg) const { | |
93 return getPhys(virtReg) != NO_PHYS_REG; | |
94 } | |
95 | |
96 /// @brief returns the physical register mapped to the specified | |
97 /// virtual register | |
98 unsigned getPhys(unsigned virtReg) const { | |
99 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); | |
100 return Virt2PhysMap[virtReg]; | |
101 } | |
102 | |
103 /// @brief creates a mapping for the specified virtual register to | |
104 /// the specified physical register | |
105 void assignVirt2Phys(unsigned virtReg, unsigned physReg) { | |
106 assert(TargetRegisterInfo::isVirtualRegister(virtReg) && | |
107 TargetRegisterInfo::isPhysicalRegister(physReg)); | |
108 assert(Virt2PhysMap[virtReg] == NO_PHYS_REG && | |
109 "attempt to assign physical register to already mapped " | |
110 "virtual register"); | |
111 Virt2PhysMap[virtReg] = physReg; | |
112 } | |
113 | |
114 /// @brief clears the specified virtual register's, physical | |
115 /// register mapping | |
116 void clearVirt(unsigned virtReg) { | |
117 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); | |
118 assert(Virt2PhysMap[virtReg] != NO_PHYS_REG && | |
119 "attempt to clear a not assigned virtual register"); | |
120 Virt2PhysMap[virtReg] = NO_PHYS_REG; | |
121 } | |
122 | |
123 /// @brief clears all virtual to physical register mappings | |
124 void clearAllVirt() { | |
125 Virt2PhysMap.clear(); | |
126 grow(); | |
127 } | |
128 | |
129 /// @brief returns true if VirtReg is assigned to its preferred physreg. | |
130 bool hasPreferredPhys(unsigned VirtReg); | |
131 | |
132 /// @brief returns true if VirtReg has a known preferred register. | |
133 /// This returns false if VirtReg has a preference that is a virtual | |
134 /// register that hasn't been assigned yet. | |
135 bool hasKnownPreference(unsigned VirtReg); | |
136 | |
137 /// @brief records virtReg is a split live interval from SReg. | |
138 void setIsSplitFromReg(unsigned virtReg, unsigned SReg) { | |
139 Virt2SplitMap[virtReg] = SReg; | |
140 } | |
141 | |
142 /// @brief returns the live interval virtReg is split from. | |
143 unsigned getPreSplitReg(unsigned virtReg) const { | |
144 return Virt2SplitMap[virtReg]; | |
145 } | |
146 | |
147 /// getOriginal - Return the original virtual register that VirtReg descends | |
148 /// from through splitting. | |
149 /// A register that was not created by splitting is its own original. | |
150 /// This operation is idempotent. | |
151 unsigned getOriginal(unsigned VirtReg) const { | |
152 unsigned Orig = getPreSplitReg(VirtReg); | |
153 return Orig ? Orig : VirtReg; | |
154 } | |
155 | |
156 /// @brief returns true if the specified virtual register is not | |
157 /// mapped to a stack slot or rematerialized. | |
158 bool isAssignedReg(unsigned virtReg) const { | |
159 if (getStackSlot(virtReg) == NO_STACK_SLOT) | |
160 return true; | |
161 // Split register can be assigned a physical register as well as a | |
162 // stack slot or remat id. | |
163 return (Virt2SplitMap[virtReg] && Virt2PhysMap[virtReg] != NO_PHYS_REG); | |
164 } | |
165 | |
166 /// @brief returns the stack slot mapped to the specified virtual | |
167 /// register | |
168 int getStackSlot(unsigned virtReg) const { | |
169 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); | |
170 return Virt2StackSlotMap[virtReg]; | |
171 } | |
172 | |
173 /// @brief create a mapping for the specifed virtual register to | |
174 /// the next available stack slot | |
175 int assignVirt2StackSlot(unsigned virtReg); | |
176 /// @brief create a mapping for the specified virtual register to | |
177 /// the specified stack slot | |
178 void assignVirt2StackSlot(unsigned virtReg, int frameIndex); | |
179 | |
180 void print(raw_ostream &OS, const Module* M = 0) const; | |
181 void dump() const; | |
182 }; | |
183 | |
184 inline raw_ostream &operator<<(raw_ostream &OS, const VirtRegMap &VRM) { | |
185 VRM.print(OS); | |
186 return OS; | |
187 } | |
188 } // End llvm namespace | |
189 | |
190 #endif |