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comparison lib/Target/Mips/Mips16InstrInfo.h @ 0:95c75e76d11b LLVM3.4

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LLVM 3.4
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Thu, 12 Dec 2013 13:56:28 +0900
parents
children e4204d083e25
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-1:000000000000 0:95c75e76d11b
1 //===-- Mips16InstrInfo.h - Mips16 Instruction Information ------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips16 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef MIPS16INSTRUCTIONINFO_H
15 #define MIPS16INSTRUCTIONINFO_H
16
17 #include "Mips16RegisterInfo.h"
18 #include "MipsInstrInfo.h"
19
20 namespace llvm {
21
22 class Mips16InstrInfo : public MipsInstrInfo {
23 const Mips16RegisterInfo RI;
24
25 public:
26 explicit Mips16InstrInfo(MipsTargetMachine &TM);
27
28 virtual const MipsRegisterInfo &getRegisterInfo() const;
29
30 /// isLoadFromStackSlot - If the specified machine instruction is a direct
31 /// load from a stack slot, return the virtual or physical register number of
32 /// the destination along with the FrameIndex of the loaded stack slot. If
33 /// not, return 0. This predicate must return 0 if the instruction has
34 /// any side effects other than loading from the stack slot.
35 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
36 int &FrameIndex) const;
37
38 /// isStoreToStackSlot - If the specified machine instruction is a direct
39 /// store to a stack slot, return the virtual or physical register number of
40 /// the source reg along with the FrameIndex of the loaded stack slot. If
41 /// not, return 0. This predicate must return 0 if the instruction has
42 /// any side effects other than storing to the stack slot.
43 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
44 int &FrameIndex) const;
45
46 virtual void copyPhysReg(MachineBasicBlock &MBB,
47 MachineBasicBlock::iterator MI, DebugLoc DL,
48 unsigned DestReg, unsigned SrcReg,
49 bool KillSrc) const;
50
51 virtual void storeRegToStack(MachineBasicBlock &MBB,
52 MachineBasicBlock::iterator MBBI,
53 unsigned SrcReg, bool isKill, int FrameIndex,
54 const TargetRegisterClass *RC,
55 const TargetRegisterInfo *TRI,
56 int64_t Offset) const;
57
58 virtual void loadRegFromStack(MachineBasicBlock &MBB,
59 MachineBasicBlock::iterator MBBI,
60 unsigned DestReg, int FrameIndex,
61 const TargetRegisterClass *RC,
62 const TargetRegisterInfo *TRI,
63 int64_t Offset) const;
64
65 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
66
67 virtual unsigned getOppositeBranchOpc(unsigned Opc) const;
68
69 // Adjust SP by FrameSize bytes. Save RA, S0, S1
70 void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
71 MachineBasicBlock::iterator I) const;
72
73 // Adjust SP by FrameSize bytes. Restore RA, S0, S1
74 void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
75 MachineBasicBlock::iterator I) const;
76
77
78 /// Adjust SP by Amount bytes.
79 void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
80 MachineBasicBlock::iterator I) const;
81
82 /// Emit a series of instructions to load an immediate.
83 // This is to adjust some FrameReg. We return the new register to be used
84 // in place of FrameReg and the adjusted immediate field (&NewImm)
85 //
86 unsigned loadImmediate(unsigned FrameReg,
87 int64_t Imm, MachineBasicBlock &MBB,
88 MachineBasicBlock::iterator II, DebugLoc DL,
89 unsigned &NewImm) const;
90
91 unsigned basicLoadImmediate(unsigned FrameReg,
92 int64_t Imm, MachineBasicBlock &MBB,
93 MachineBasicBlock::iterator II, DebugLoc DL,
94 unsigned &NewImm) const;
95
96 static bool validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount);
97
98 static bool validSpImm8(int offset) {
99 return ((offset & 7) == 0) && isInt<11>(offset);
100 }
101
102 //
103 // build the proper one based on the Imm field
104 //
105
106 const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
107
108 void BuildAddiuSpImm
109 (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const;
110
111 unsigned getInlineAsmLength(const char *Str,
112 const MCAsmInfo &MAI) const;
113 private:
114 virtual unsigned getAnalyzableBrOpc(unsigned Opc) const;
115
116 void ExpandRetRA16(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
117 unsigned Opc) const;
118
119 // Adjust SP by Amount bytes where bytes can be up to 32bit number.
120 void adjustStackPtrBig(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
121 MachineBasicBlock::iterator I,
122 unsigned Reg1, unsigned Reg2) const;
123
124 // Adjust SP by Amount bytes where bytes can be up to 32bit number.
125 void adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
126 MachineBasicBlock &MBB,
127 MachineBasicBlock::iterator I) const;
128
129 };
130
131 }
132
133 #endif