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comparison lib/Target/Mips/MipsInstrInfo.h @ 0:95c75e76d11b LLVM3.4

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LLVM 3.4
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Thu, 12 Dec 2013 13:56:28 +0900
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children 54457678186b
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-1:000000000000 0:95c75e76d11b
1 //===-- MipsInstrInfo.h - Mips Instruction Information ----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef MIPSINSTRUCTIONINFO_H
15 #define MIPSINSTRUCTIONINFO_H
16
17 #include "Mips.h"
18 #include "MipsAnalyzeImmediate.h"
19 #include "MipsRegisterInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23
24 #define GET_INSTRINFO_HEADER
25 #include "MipsGenInstrInfo.inc"
26
27 namespace llvm {
28
29 class MipsInstrInfo : public MipsGenInstrInfo {
30 virtual void anchor();
31 protected:
32 MipsTargetMachine &TM;
33 unsigned UncondBrOpc;
34
35 public:
36 enum BranchType {
37 BT_None, // Couldn't analyze branch.
38 BT_NoBranch, // No branches found.
39 BT_Uncond, // One unconditional branch.
40 BT_Cond, // One conditional branch.
41 BT_CondUncond, // A conditional branch followed by an unconditional branch.
42 BT_Indirect // One indirct branch.
43 };
44
45 explicit MipsInstrInfo(MipsTargetMachine &TM, unsigned UncondBrOpc);
46
47 static const MipsInstrInfo *create(MipsTargetMachine &TM);
48
49 /// Branch Analysis
50 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
51 MachineBasicBlock *&FBB,
52 SmallVectorImpl<MachineOperand> &Cond,
53 bool AllowModify) const;
54
55 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
56
57 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
58 MachineBasicBlock *FBB,
59 const SmallVectorImpl<MachineOperand> &Cond,
60 DebugLoc DL) const;
61
62 virtual
63 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
64
65 BranchType AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
66 MachineBasicBlock *&FBB,
67 SmallVectorImpl<MachineOperand> &Cond,
68 bool AllowModify,
69 SmallVectorImpl<MachineInstr*> &BranchInstrs) const;
70
71 /// Insert nop instruction when hazard condition is found
72 virtual void insertNoop(MachineBasicBlock &MBB,
73 MachineBasicBlock::iterator MI) const;
74
75 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
76 /// such, whenever a client has an instance of instruction info, it should
77 /// always be able to get register info as well (through this method).
78 ///
79 virtual const MipsRegisterInfo &getRegisterInfo() const = 0;
80
81 virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;
82
83 /// Return the number of bytes of code the specified instruction may be.
84 unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
85
86 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
87 MachineBasicBlock::iterator MBBI,
88 unsigned SrcReg, bool isKill, int FrameIndex,
89 const TargetRegisterClass *RC,
90 const TargetRegisterInfo *TRI) const {
91 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0);
92 }
93
94 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
95 MachineBasicBlock::iterator MBBI,
96 unsigned DestReg, int FrameIndex,
97 const TargetRegisterClass *RC,
98 const TargetRegisterInfo *TRI) const {
99 loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
100 }
101
102 virtual void storeRegToStack(MachineBasicBlock &MBB,
103 MachineBasicBlock::iterator MI,
104 unsigned SrcReg, bool isKill, int FrameIndex,
105 const TargetRegisterClass *RC,
106 const TargetRegisterInfo *TRI,
107 int64_t Offset) const = 0;
108
109 virtual void loadRegFromStack(MachineBasicBlock &MBB,
110 MachineBasicBlock::iterator MI,
111 unsigned DestReg, int FrameIndex,
112 const TargetRegisterClass *RC,
113 const TargetRegisterInfo *TRI,
114 int64_t Offset) const = 0;
115
116 /// Create an instruction which has the same operands and memory operands
117 /// as MI but has a new opcode.
118 MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
119 MachineBasicBlock::iterator I) const;
120
121 protected:
122 bool isZeroImm(const MachineOperand &op) const;
123
124 MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI,
125 unsigned Flag) const;
126
127 private:
128 virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0;
129
130 void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
131 MachineBasicBlock *&BB,
132 SmallVectorImpl<MachineOperand> &Cond) const;
133
134 void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL,
135 const SmallVectorImpl<MachineOperand>& Cond) const;
136 };
137
138 /// Create MipsInstrInfo objects.
139 const MipsInstrInfo *createMips16InstrInfo(MipsTargetMachine &TM);
140 const MipsInstrInfo *createMipsSEInstrInfo(MipsTargetMachine &TM);
141
142 }
143
144 #endif