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comparison lib/Target/NVPTX/NVPTXISelLowering.h @ 0:95c75e76d11b LLVM3.4

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LLVM 3.4
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Thu, 12 Dec 2013 13:56:28 +0900
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children 54457678186b
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-1:000000000000 0:95c75e76d11b
1 //===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that NVPTX uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #ifndef NVPTXISELLOWERING_H
16 #define NVPTXISELLOWERING_H
17
18 #include "NVPTX.h"
19 #include "NVPTXSubtarget.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
22
23 namespace llvm {
24 namespace NVPTXISD {
25 enum NodeType {
26 // Start the numbering from where ISD NodeType finishes.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
28 Wrapper,
29 CALL,
30 RET_FLAG,
31 LOAD_PARAM,
32 DeclareParam,
33 DeclareScalarParam,
34 DeclareRetParam,
35 DeclareRet,
36 DeclareScalarRet,
37 PrintCall,
38 PrintCallUni,
39 CallArgBegin,
40 CallArg,
41 LastCallArg,
42 CallArgEnd,
43 CallVoid,
44 CallVal,
45 CallSymbol,
46 Prototype,
47 MoveParam,
48 PseudoUseParam,
49 RETURN,
50 CallSeqBegin,
51 CallSeqEnd,
52 CallPrototype,
53 Dummy,
54
55 LoadV2 = ISD::FIRST_TARGET_MEMORY_OPCODE,
56 LoadV4,
57 LDGV2, // LDG.v2
58 LDGV4, // LDG.v4
59 LDUV2, // LDU.v2
60 LDUV4, // LDU.v4
61 StoreV2,
62 StoreV4,
63 LoadParam,
64 LoadParamV2,
65 LoadParamV4,
66 StoreParam,
67 StoreParamV2,
68 StoreParamV4,
69 StoreParamS32, // to sext and store a <32bit value, not used currently
70 StoreParamU32, // to zext and store a <32bit value, not used currently
71 StoreRetval,
72 StoreRetvalV2,
73 StoreRetvalV4
74 };
75 }
76
77 //===--------------------------------------------------------------------===//
78 // TargetLowering Implementation
79 //===--------------------------------------------------------------------===//
80 class NVPTXTargetLowering : public TargetLowering {
81 public:
82 explicit NVPTXTargetLowering(NVPTXTargetMachine &TM);
83 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
84
85 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
86 SDValue LowerGlobalAddress(const GlobalValue *GV, int64_t Offset,
87 SelectionDAG &DAG) const;
88
89 virtual const char *getTargetNodeName(unsigned Opcode) const;
90
91 bool isTypeSupportedInIntrinsic(MVT VT) const;
92
93 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
94 unsigned Intrinsic) const;
95
96 /// isLegalAddressingMode - Return true if the addressing mode represented
97 /// by AM is legal for this target, for a load/store of the specified type
98 /// Used to guide target specific optimizations, like loop strength
99 /// reduction (LoopStrengthReduce.cpp) and memory optimization for
100 /// address mode (CodeGenPrepare.cpp)
101 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
102
103 /// getFunctionAlignment - Return the Log2 alignment of this function.
104 virtual unsigned getFunctionAlignment(const Function *F) const;
105
106 virtual EVT getSetCCResultType(LLVMContext &, EVT VT) const {
107 if (VT.isVector())
108 return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
109 return MVT::i1;
110 }
111
112 ConstraintType getConstraintType(const std::string &Constraint) const;
113 std::pair<unsigned, const TargetRegisterClass *>
114 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
115
116 virtual SDValue LowerFormalArguments(
117 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
118 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
119 SmallVectorImpl<SDValue> &InVals) const;
120
121 virtual SDValue
122 LowerCall(CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const;
123
124 std::string getPrototype(Type *, const ArgListTy &,
125 const SmallVectorImpl<ISD::OutputArg> &,
126 unsigned retAlignment,
127 const ImmutableCallSite *CS) const;
128
129 virtual SDValue
130 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
131 const SmallVectorImpl<ISD::OutputArg> &Outs,
132 const SmallVectorImpl<SDValue> &OutVals, SDLoc dl,
133 SelectionDAG &DAG) const;
134
135 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
136 std::vector<SDValue> &Ops,
137 SelectionDAG &DAG) const;
138
139 NVPTXTargetMachine *nvTM;
140
141 // PTX always uses 32-bit shift amounts
142 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
143
144 virtual bool shouldSplitVectorElementType(EVT VT) const;
145
146 private:
147 const NVPTXSubtarget &nvptxSubtarget; // cache the subtarget here
148
149 SDValue getExtSymb(SelectionDAG &DAG, const char *name, int idx,
150 EVT = MVT::i32) const;
151 SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT) const;
152 SDValue getParamHelpSymbol(SelectionDAG &DAG, int idx);
153
154 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
155
156 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
157 SDValue LowerLOADi1(SDValue Op, SelectionDAG &DAG) const;
158
159 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
160 SDValue LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const;
161 SDValue LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const;
162
163 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
164 SelectionDAG &DAG) const;
165
166 unsigned getArgumentAlignment(SDValue Callee, const ImmutableCallSite *CS,
167 Type *Ty, unsigned Idx) const;
168 };
169 } // namespace llvm
170
171 #endif // NVPTXISELLOWERING_H