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comparison test/CodeGen/R600/mad_uint24.ll @ 0:95c75e76d11b LLVM3.4

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LLVM 3.4
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Thu, 12 Dec 2013 13:56:28 +0900
parents
children 54457678186b
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-1:000000000000 0:95c75e76d11b
1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK
2 ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG-CHECK
3 ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
4
5 ; EG-CHECK-LABEL: @u32_mad24
6 ; EG-CHECK: MULADD_UINT24 {{[* ]*}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, KC0[2].W, KC0[3].X
7 ; SI-CHECK-LABEL: @u32_mad24
8 ; SI-CHECK: V_MAD_U32_U24
9
10 define void @u32_mad24(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
11 entry:
12 %0 = shl i32 %a, 8
13 %a_24 = lshr i32 %0, 8
14 %1 = shl i32 %b, 8
15 %b_24 = lshr i32 %1, 8
16 %2 = mul i32 %a_24, %b_24
17 %3 = add i32 %2, %c
18 store i32 %3, i32 addrspace(1)* %out
19 ret void
20 }
21
22 ; EG-CHECK-LABEL: @i16_mad24
23 ; EG-CHECK-DAG: VTX_READ_16 [[A:T[0-9]\.X]], T{{[0-9]}}.X, 40
24 ; EG-CHECK-DAG: VTX_READ_16 [[B:T[0-9]\.X]], T{{[0-9]}}.X, 44
25 ; EG-CHECK-DAG: VTX_READ_16 [[C:T[0-9]\.X]], T{{[0-9]}}.X, 48
26 ; The order of A and B does not matter.
27 ; EG-CHECK: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]], [[A]], [[B]], [[C]]
28 ; The result must be sign-extended
29 ; EG-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], PV.[[MAD_CHAN]], literal.x
30 ; EG-CHECK: 16
31 ; EG-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]], literal.x
32 ; EG-CHECK: 16
33 ; SI-CHECK-LABEL: @i16_mad24
34 ; SI-CHECK: V_MAD_U32_U24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
35 ; SI-CHECK: V_LSHLREV_B32_e32 [[LSHL:v[0-9]]], 16, [[MAD]]
36 ; SI-CHECK: V_ASHRREV_I32_e32 v{{[0-9]}}, 16, [[LSHL]]
37
38 define void @i16_mad24(i32 addrspace(1)* %out, i16 %a, i16 %b, i16 %c) {
39 entry:
40 %0 = mul i16 %a, %b
41 %1 = add i16 %0, %c
42 %2 = sext i16 %1 to i32
43 store i32 %2, i32 addrspace(1)* %out
44 ret void
45 }
46
47 ; EG-CHECK-LABEL: @i8_mad24
48 ; EG-CHECK-DAG: VTX_READ_8 [[A:T[0-9]\.X]], T{{[0-9]}}.X, 40
49 ; EG-CHECK-DAG: VTX_READ_8 [[B:T[0-9]\.X]], T{{[0-9]}}.X, 44
50 ; EG-CHECK-DAG: VTX_READ_8 [[C:T[0-9]\.X]], T{{[0-9]}}.X, 48
51 ; The order of A and B does not matter.
52 ; EG-CHECK: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]], [[A]], [[B]], [[C]]
53 ; The result must be sign-extended
54 ; EG-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], PV.[[MAD_CHAN]], literal.x
55 ; EG-CHECK: 24
56 ; EG-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]], literal.x
57 ; EG-CHECK: 24
58 ; SI-CHECK-LABEL: @i8_mad24
59 ; SI-CHECK: V_MAD_U32_U24 [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
60 ; SI-CHECK: V_LSHLREV_B32_e32 [[LSHL:v[0-9]]], 24, [[MUL]]
61 ; SI-CHECK: V_ASHRREV_I32_e32 v{{[0-9]}}, 24, [[LSHL]]
62
63 define void @i8_mad24(i32 addrspace(1)* %out, i8 %a, i8 %b, i8 %c) {
64 entry:
65 %0 = mul i8 %a, %b
66 %1 = add i8 %0, %c
67 %2 = sext i8 %1 to i32
68 store i32 %2, i32 addrspace(1)* %out
69 ret void
70 }