Mercurial > hg > CbC > CbC_llvm

comparison lib/Target/Hexagon/HexagonIntrinsics.td @ 95:afa8332a0e37 LLVM3.8

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents 60c9769439b8
children 7d135dc70f03
comparison
equal deleted inserted replaced
84:f3e34b893a5f 95:afa8332a0e37
674 (A2_tfrih IntRegs:$Rs, u16_0ImmPred:$Is)>; 674 (A2_tfrih IntRegs:$Rs, u16_0ImmPred:$Is)>;
675 675
676 // Transfer Register/immediate. 676 // Transfer Register/immediate.
677 def : T_R_pat <A2_tfr, int_hexagon_A2_tfr>; 677 def : T_R_pat <A2_tfr, int_hexagon_A2_tfr>;
678 def : T_I_pat <A2_tfrsi, int_hexagon_A2_tfrsi>; 678 def : T_I_pat <A2_tfrsi, int_hexagon_A2_tfrsi>;
679 def : T_I_pat <A2_tfrpi, int_hexagon_A2_tfrpi>;
679 680
680 // Assembler mapped from Rdd32=Rss32 to Rdd32=combine(Rss.H32,Rss.L32) 681 // Assembler mapped from Rdd32=Rss32 to Rdd32=combine(Rss.H32,Rss.L32)
681 def : Pat<(int_hexagon_A2_tfrp DoubleRegs:$src), 682 def : Pat<(int_hexagon_A2_tfrp DoubleRegs:$src),
682 (A2_combinew (HiReg DoubleRegs:$src), (LoReg DoubleRegs:$src))>; 683 (A2_combinew (HiReg DoubleRegs:$src), (LoReg DoubleRegs:$src))>;
683 684
690 def: T_RR_pat<A2_combine_lh, int_hexagon_A2_combine_lh>; 691 def: T_RR_pat<A2_combine_lh, int_hexagon_A2_combine_lh>;
691 def: T_RR_pat<A2_combine_ll, int_hexagon_A2_combine_ll>; 692 def: T_RR_pat<A2_combine_ll, int_hexagon_A2_combine_ll>;
692 693
693 def: T_II_pat<A2_combineii, int_hexagon_A2_combineii, s8ExtPred, s8ImmPred>; 694 def: T_II_pat<A2_combineii, int_hexagon_A2_combineii, s8ExtPred, s8ImmPred>;
694 695
695 def: Pat<(i32 (int_hexagon_C2_mux (I32:$Rp), (I32:$Rs), 696 def: Pat<(i32 (int_hexagon_C2_mux (I32:$Rp), (I32:$Rs), (I32:$Rt))),
696 (I32:$Rt))),
697 (i32 (C2_mux (C2_tfrrp IntRegs:$Rp), IntRegs:$Rs, IntRegs:$Rt))>; 697 (i32 (C2_mux (C2_tfrrp IntRegs:$Rp), IntRegs:$Rs, IntRegs:$Rt))>;
698 698
699 // Mux 699 // Mux
700 def : T_QRI_pat<C2_muxir, int_hexagon_C2_muxir, s8ExtPred>; 700 def : T_QRI_pat<C2_muxir, int_hexagon_C2_muxir, s8ExtPred>;
701 def : T_QIR_pat<C2_muxri, int_hexagon_C2_muxri, s8ExtPred>; 701 def : T_QIR_pat<C2_muxri, int_hexagon_C2_muxri, s8ExtPred>;
921 def: qi_CRInst_qiqi_pat<C2_and, int_hexagon_C2_and>; 921 def: qi_CRInst_qiqi_pat<C2_and, int_hexagon_C2_and>;
922 def: qi_CRInst_qiqi_pat<C2_andn, int_hexagon_C2_andn>; 922 def: qi_CRInst_qiqi_pat<C2_andn, int_hexagon_C2_andn>;
923 def: qi_CRInst_qiqi_pat<C2_or, int_hexagon_C2_or>; 923 def: qi_CRInst_qiqi_pat<C2_or, int_hexagon_C2_or>;
924 def: qi_CRInst_qiqi_pat<C2_orn, int_hexagon_C2_orn>; 924 def: qi_CRInst_qiqi_pat<C2_orn, int_hexagon_C2_orn>;
925 def: qi_CRInst_qiqi_pat<C2_xor, int_hexagon_C2_xor>; 925 def: qi_CRInst_qiqi_pat<C2_xor, int_hexagon_C2_xor>;
926
927 // Assembler mapped from Pd4=Ps4 to Pd4=or(Ps4,Ps4)
928 def : Pat<(int_hexagon_C2_pxfer_map PredRegs:$src),
929 (C2_pxfer_map PredRegs:$src)>;
926 930
927 // Multiply 32x32 and use lower result 931 // Multiply 32x32 and use lower result
928 def : T_RRI_pat <M2_macsip, int_hexagon_M2_macsip>; 932 def : T_RRI_pat <M2_macsip, int_hexagon_M2_macsip>;
929 def : T_RRI_pat <M2_macsin, int_hexagon_M2_macsin>; 933 def : T_RRI_pat <M2_macsin, int_hexagon_M2_macsin>;
930 def : T_RRR_pat <M2_maci, int_hexagon_M2_maci>; 934 def : T_RRR_pat <M2_maci, int_hexagon_M2_maci>;
1256 def: Pat<(i32 (int_hexagon_S2_storew_locked (I32:$Rs), (I32:$Rt))), 1260 def: Pat<(i32 (int_hexagon_S2_storew_locked (I32:$Rs), (I32:$Rt))),
1257 (i32 (C2_tfrpr (S2_storew_locked (I32:$Rs), (I32:$Rt))))>; 1261 (i32 (C2_tfrpr (S2_storew_locked (I32:$Rs), (I32:$Rt))))>;
1258 def: Pat<(i32 (int_hexagon_S4_stored_locked (I32:$Rs), (I64:$Rt))), 1262 def: Pat<(i32 (int_hexagon_S4_stored_locked (I32:$Rs), (I64:$Rt))),
1259 (i32 (C2_tfrpr (S4_stored_locked (I32:$Rs), (I64:$Rt))))>; 1263 (i32 (C2_tfrpr (S4_stored_locked (I32:$Rs), (I64:$Rt))))>;
1260 1264
1265 /********************************************************************
1266 * ST
1267 *********************************************************************/
1268
1269 class T_stb_pat <InstHexagon MI, Intrinsic IntID, PatLeaf Val>
1270 : Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru),
1271 (MI I32:$Rs, Val:$Rt, I32:$Ru)>;
1272
1273 def : T_stb_pat <S2_storerh_pbr_pseudo, int_hexagon_brev_sth, I32>;
1274 def : T_stb_pat <S2_storerb_pbr_pseudo, int_hexagon_brev_stb, I32>;
1275 def : T_stb_pat <S2_storeri_pbr_pseudo, int_hexagon_brev_stw, I32>;
1276 def : T_stb_pat <S2_storerf_pbr_pseudo, int_hexagon_brev_sthhi, I32>;
1277 def : T_stb_pat <S2_storerd_pbr_pseudo, int_hexagon_brev_std, I64>;
1278
1279 class T_stc_pat <InstHexagon MI, Intrinsic IntID, PatLeaf Imm, PatLeaf Val>
1280 : Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru, Imm:$s),
1281 (MI I32:$Rs, Val:$Rt, I32:$Ru, Imm:$s)>;
1282
1283 def: T_stc_pat<S2_storerb_pci_pseudo, int_hexagon_circ_stb, s4_0ImmPred, I32>;
1284 def: T_stc_pat<S2_storerh_pci_pseudo, int_hexagon_circ_sth, s4_1ImmPred, I32>;
1285 def: T_stc_pat<S2_storeri_pci_pseudo, int_hexagon_circ_stw, s4_2ImmPred, I32>;
1286 def: T_stc_pat<S2_storerd_pci_pseudo, int_hexagon_circ_std, s4_3ImmPred, I64>;
1287 def: T_stc_pat<S2_storerf_pci_pseudo, int_hexagon_circ_sthhi, s4_1ImmPred, I32>;
1288
1261 include "HexagonIntrinsicsV3.td" 1289 include "HexagonIntrinsicsV3.td"
1262 include "HexagonIntrinsicsV4.td" 1290 include "HexagonIntrinsicsV4.td"
1263 include "HexagonIntrinsicsV5.td" 1291 include "HexagonIntrinsicsV5.td"